Intel 253668-032US Benutzerhandbuch
2-8 Vol. 3
SYSTEM ARCHITECTURE OVERVIEW
The IDTR register is expanded to hold a 64-bit base address. Task gates are not
supported.
supported.
2.1.5 Memory
Management
System architecture supports either direct physical addressing of memory or virtual
memory (through paging). When physical addressing is used, a linear address is
treated as a physical address. When paging is used: all code, data, stack, and system
segments (including the GDT and IDT) can be paged with only the most recently
accessed pages being held in physical memory.
The location of pages (sometimes called page frames) in physical memory is
contained in the paging structures. These structures reside in physical memory (see
Figure 2-1 for the case of 32-bit paging).
The base physical address of the paging-structure hierarchy is contained in control
register CR3. The entries in the paging structures determine the physical address of
the base of a page frame, access rights and memory management information.
To use this paging mechanism, a linear address is broken into parts. The parts
provide separate offsets into the paging structures and the page frame. A system can
have a single hierarchy of paging structures or several. For example, each task can
have its own hierarchy.
memory (through paging). When physical addressing is used, a linear address is
treated as a physical address. When paging is used: all code, data, stack, and system
segments (including the GDT and IDT) can be paged with only the most recently
accessed pages being held in physical memory.
The location of pages (sometimes called page frames) in physical memory is
contained in the paging structures. These structures reside in physical memory (see
Figure 2-1 for the case of 32-bit paging).
The base physical address of the paging-structure hierarchy is contained in control
register CR3. The entries in the paging structures determine the physical address of
the base of a page frame, access rights and memory management information.
To use this paging mechanism, a linear address is broken into parts. The parts
provide separate offsets into the paging structures and the page frame. A system can
have a single hierarchy of paging structures or several. For example, each task can
have its own hierarchy.
2.1.5.1
Memory Management in IA-32e Mode
In IA-32e mode, physical memory pages are managed by a set of system data struc-
tures. In compatibility mode and 64-bit mode, four levels of system data structures
are used. These include:
tures. In compatibility mode and 64-bit mode, four levels of system data structures
are used. These include:
•
The page map level 4 (PML4) — An entry in a PML4 table contains the physical
address of the base of a page directory pointer table, access rights, and memory
management information. The base physical address of the PML4 is stored in
CR3.
address of the base of a page directory pointer table, access rights, and memory
management information. The base physical address of the PML4 is stored in
CR3.
•
A set of page directory pointer tables — An entry in a page directory pointer
table contains the physical address of the base of a page directory table, access
rights, and memory management information.
table contains the physical address of the base of a page directory table, access
rights, and memory management information.
•
Sets of page directories — An entry in a page directory table contains the
physical address of the base of a page table, access rights, and memory
management information.
physical address of the base of a page table, access rights, and memory
management information.
•
Sets of page tables — An entry in a page table contains the physical address of
a page frame, access rights, and memory management information.
a page frame, access rights, and memory management information.