Intel 253668-032US Benutzerhandbuch
Vol. 3 16-1
CHAPTER 16
DEBUGGING, PROFILING BRANCHES AND TIME-
STAMP COUNTER
Intel 64 and IA-32 architectures provide debug facilities for use in debugging code
and monitoring performance. These facilities are valuable for debugging application
software, system software, and multitasking operating systems. Debug support is
accessed using debug registers (DB0 through DB7) and model-specific registers
(MSRs):
and monitoring performance. These facilities are valuable for debugging application
software, system software, and multitasking operating systems. Debug support is
accessed using debug registers (DB0 through DB7) and model-specific registers
(MSRs):
•
Debug registers hold the addresses of memory and I/O locations called break-
points. Breakpoints are user-selected locations in a program, a data-storage area
in memory, or specific I/O ports. They are set where a programmer or system
designer wishes to halt execution of a program and examine the state of the
processor by invoking debugger software. A debug exception (#DB) is generated
when a memory or I/O access is made to a breakpoint address.
points. Breakpoints are user-selected locations in a program, a data-storage area
in memory, or specific I/O ports. They are set where a programmer or system
designer wishes to halt execution of a program and examine the state of the
processor by invoking debugger software. A debug exception (#DB) is generated
when a memory or I/O access is made to a breakpoint address.
•
MSRs monitor branches, interrupts, and exceptions; they record addresses of the
last branch, interrupt or exception taken and the last branch taken before an
interrupt or exception.
last branch, interrupt or exception taken and the last branch taken before an
interrupt or exception.
16.1
OVERVIEW OF DEBUG SUPPORT FACILITIES
The following processor facilities support debugging and performance monitoring:
•
Debug exception (#DB) — Transfers program control to a debug procedure or
task when a debug event occurs.
task when a debug event occurs.
•
Breakpoint exception (#BP) — See breakpoint instruction (INT 3) below.
•
Breakpoint-address registers (DR0 through DR3) — Specifies the
addresses of up to 4 breakpoints.
addresses of up to 4 breakpoints.
•
Debug status register (DR6) — Reports the conditions that were in effect
when a debug or breakpoint exception was generated.
when a debug or breakpoint exception was generated.
•
Debug control register (DR7) — Specifies the forms of memory or I/O access
that cause breakpoints to be generated.
that cause breakpoints to be generated.
•
T (trap) flag, TSS — Generates a debug exception (#DB) when an attempt is
made to switch to a task with the T flag set in its TSS.
made to switch to a task with the T flag set in its TSS.
•
RF (resume) flag, EFLAGS register — Suppresses multiple exceptions to the
same instruction.
same instruction.
•
TF (trap) flag, EFLAGS register — Generates a debug exception (#DB) after
every execution of an instruction.
every execution of an instruction.
•
Breakpoint instruction (INT 3) — Generates a breakpoint exception (#BP)
that transfers program control to the debugger procedure or task. This
that transfers program control to the debugger procedure or task. This