Intel 253668-032US Benutzerhandbuch
16-6 Vol. 3
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
10 — Break on I/O reads or writes.
11 — Break on data reads or writes but not instruction fetches.
11 — Break on data reads or writes but not instruction fetches.
When the DE flag is clear, the processor interprets the R/Wn bits the same as for
the Intel386™ and Intel486™ processors, which is as follows:
the Intel386™ and Intel486™ processors, which is as follows:
00 — Break on instruction execution only.
01 — Break on data writes only.
10 — Undefined.
11 — Break on data reads or writes but not instruction fetches.
01 — Break on data writes only.
10 — Undefined.
11 — Break on data reads or writes but not instruction fetches.
•
LEN0 through LEN3 (Length) fields (bits 18, 19, 22, 23, 26, 27, 30, and
31) — Specify the size of the memory location at the address specified in the
corresponding breakpoint address register (DR0 through DR3). These fields are
interpreted as follows:
31) — Specify the size of the memory location at the address specified in the
corresponding breakpoint address register (DR0 through DR3). These fields are
interpreted as follows:
00 — 1-byte length.
01 — 2-byte length.
10 — Undefined (or 8 byte length, see note below).
11 — 4-byte length.
01 — 2-byte length.
10 — Undefined (or 8 byte length, see note below).
11 — 4-byte length.
If the corresponding RWn field in register DR7 is 00 (instruction execution), then the
LENn field should also be 00. The effect of using other lengths is undefined. See
Section 16.2.5, “Breakpoint Field Recognition,” below.
LENn field should also be 00. The effect of using other lengths is undefined. See
Section 16.2.5, “Breakpoint Field Recognition,” below.
NOTES
For Pentium
®
4 and Intel
®
Xeon
®
processors with a CPUID signature
corresponding to family 15 (model 3, 4, and 6), break point
conditions permit specifying 8-byte length on data read/write with an
of encoding 10B in the LENn field.
Encoding 10B is also supported in processors based on Intel Core
microarchitecture or enhanced Intel Core microarchitecture, the
respective CPUID signatures corresponding to family 6, model 15,
and family 6, display_model value 23. The Encoding 10B is supported
in processors based on Intel Atom microarchitecture, with CPUID
signature of family 6, display_model value 28. The encoding 10B is
undefined for other processors.
conditions permit specifying 8-byte length on data read/write with an
of encoding 10B in the LENn field.
Encoding 10B is also supported in processors based on Intel Core
microarchitecture or enhanced Intel Core microarchitecture, the
respective CPUID signatures corresponding to family 6, model 15,
and family 6, display_model value 23. The Encoding 10B is supported
in processors based on Intel Atom microarchitecture, with CPUID
signature of family 6, display_model value 28. The encoding 10B is
undefined for other processors.
16.2.5
Breakpoint Field Recognition
Breakpoint address registers (debug registers DR0 through DR3) and the LENn fields
for each breakpoint define a range of sequential byte addresses for a data or I/O
breakpoint. The LENn fields permit specification of a 1-, 2-, 4-, or 8-byte range,
beginning at the linear address specified in the corresponding debug register (DRn).
Two-byte ranges must be aligned on word boundaries; 4-byte ranges must be
aligned on doubleword boundaries. I/O addresses are zero-extended (from 16 to 32
bits, for comparison with the breakpoint address in the selected debug register).
These requirements are enforced by the processor; it uses LENn field bits to mask
for each breakpoint define a range of sequential byte addresses for a data or I/O
breakpoint. The LENn fields permit specification of a 1-, 2-, 4-, or 8-byte range,
beginning at the linear address specified in the corresponding debug register (DRn).
Two-byte ranges must be aligned on word boundaries; 4-byte ranges must be
aligned on doubleword boundaries. I/O addresses are zero-extended (from 16 to 32
bits, for comparison with the breakpoint address in the selected debug register).
These requirements are enforced by the processor; it uses LENn field bits to mask