Intel 253668-032US Benutzerhandbuch
16-20 Vol. 3
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
16.4.8.1 LBR Stack and Intel
®
64 Processors
LBR MSRs are 64-bits. If IA-32e mode is disabled, only the lower 32-bits of the
address is recorded. If IA-32e mode is enabled, the processor writes 64-bit values
into the MSR.
In 64-bit mode, last branch records store 64-bit addresses; in compatibility mode,
the upper 32-bits of last branch records are cleared.
address is recorded. If IA-32e mode is enabled, the processor writes 64-bit values
into the MSR.
In 64-bit mode, last branch records store 64-bit addresses; in compatibility mode,
the upper 32-bits of last branch records are cleared.
Software should query an architectural MSR IA32_PERF_CAPABILITIES[5:0]
about the format of the address that is stored in the LBR stack. Four formats are
defined by the following encoding:
— 000000B (32-bit record format) — Stores 32-bit offset in current CS of
about the format of the address that is stored in the LBR stack. Four formats are
defined by the following encoding:
— 000000B (32-bit record format) — Stores 32-bit offset in current CS of
respective source/destination,
— 000001B (64-bit LIP record format) — Stores 64-bit linear address of
respective source/destination,
— 000010B (64-bit EIP record format) — Stores 64-bit offset (effective
address) of respective source/destination.
— 000011B (64-bit EIP record format) and Flags — Stores 64-bit offset
(effective address) of respective source/destination. LBR flags are supported
in the upper bits of ‘FROM’ register in the LBR stack. See LBR stack details
below for flag support and definition.
in the upper bits of ‘FROM’ register in the LBR stack. See LBR stack details
below for flag support and definition.
Processor’s support for the architectural MSR IA32_PERF_CAPABILITIES is
provided by CPUID.01H:ECX[PERF_CAPAB_MSR] (bit 15).
provided by CPUID.01H:ECX[PERF_CAPAB_MSR] (bit 15).
16.4.8.2 LBR Stack and IA-32 Processors
The LBR MSRs in IA-32 processors introduced prior to Intel 64 architecture store the
32-bit “To Linear Address” and “From Linear Address“ using the high and low half of
each 64-bit MSR.
32-bit “To Linear Address” and “From Linear Address“ using the high and low half of
each 64-bit MSR.
Figure 16-4. 64-bit Address Layout of LBR MSR
63
Source Address
0
0
63
Destination Address
MSR_LASTBRANCH_0_FROM_IP through MSR_LASTBRANCH_(N-1)_FROM_IP
MSR_LASTBRANCH_0_TO_IP through MSR_LASTBRANCH_(N-1)_TO_IP