Intel 253668-032US Benutzerhandbuch
Vol. 3 16-33
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
16.5.1 LBR
Stack
The last branch record stack and top-of-stack (TOS) pointer MSRs are supported
across Intel Core 2, Intel Xeon and Intel Atom processor families. Four pair of MSRs
are supported in the LBR stack
across Intel Core 2, Intel Xeon and Intel Atom processor families. Four pair of MSRs
are supported in the LBR stack
•
Last Branch Record (LBR) Stack
— MSR_LASTBRANCH_0_FROM_IP (address 40H) through
— MSR_LASTBRANCH_0_FROM_IP (address 40H) through
MSR_LASTBRANCH_3_FROM_IP (address 43H) store source addresses
— MSR_LASTBRANCH_0_TO_IP (address 60H) through
MSR_LASTBRANCH_3_To_IP (address 63H) store destination addresses.
•
Last Branch Record Top-of-Stack (TOS) Pointer — The lowest significant 2
bits of the TOS Pointer MSR (MSR_LASTBRANCH_TOS, address 1C9H) contains a
pointer to the MSR in the LBR stack that contains the most recent branch,
interrupt, or exception recorded.
bits of the TOS Pointer MSR (MSR_LASTBRANCH_TOS, address 1C9H) contains a
pointer to the MSR in the LBR stack that contains the most recent branch,
interrupt, or exception recorded.
For compatibility, the MSR_LER_TO_LIP and the MSR_LER_FROM_LIP MSRs) dupli-
cate functions of the LastExceptionToIP and LastExceptionFromIP MSRs found in P6
family processors.
cate functions of the LastExceptionToIP and LastExceptionFromIP MSRs found in P6
family processors.
16.6
LAST BRANCH, INTERRUPT, AND EXCEPTION
RECORDING (INTEL
®
CORE
™
I7 PROCESSOR FAMILY)
The Intel Core i7 processor family and Intel Xeon processors based on Intel microar-
chitecture (Nehalem) support last branch interrupt and exception recording. These
capabilities are similar to those found in Intel Core 2 processors and adds additional
capabilities:
chitecture (Nehalem) support last branch interrupt and exception recording. These
capabilities are similar to those found in Intel Core 2 processors and adds additional
capabilities:
•
Debug Trace and Branch Recording Control — The IA32_DEBUGCTL MSR
provides bit fields for software to configure mechanisms related to debug trace,
branch recording, branch trace store, and performance counter operations. See
Section 16.4.1 for a description of the flags. See Figure 16-11 for the MSR layout.
provides bit fields for software to configure mechanisms related to debug trace,
branch recording, branch trace store, and performance counter operations. See
Section 16.4.1 for a description of the flags. See Figure 16-11 for the MSR layout.
•
Last branch record (LBR) stack — There are 16 MSR pairs that store the
source and destination addresses related to recently executed branches. See
Section 16.6.1.
source and destination addresses related to recently executed branches. See
Section 16.6.1.
•
Monitoring and single-stepping of branches, exceptions, and interrupts
— See Section 16.4.2 and Section 16.4.3. In addition, the ability to freeze the
LBR stack on a PMI request is available.
— See Section 16.4.2 and Section 16.4.3. In addition, the ability to freeze the
LBR stack on a PMI request is available.
•
Branch trace messages — The IA32_DEBUGCTL MSR provides bit fields for
software to enable each logical processor to generate branch trace messages.
See Section 16.4.4. However, not all BTM messages are observable using the
Intel
software to enable each logical processor to generate branch trace messages.
See Section 16.4.4. However, not all BTM messages are observable using the
Intel
®
QPI link.
•
Last exception records — See Section 16.7.3.