Intel 253668-032US Benutzerhandbuch
Vol. 3 16-41
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
16.8
LAST BRANCH, INTERRUPT, AND EXCEPTION
RECORDING (INTEL
®
CORE
™
SOLO AND INTEL
®
CORE
™
DUO PROCESSORS)
Intel Core Solo and Intel Core Duo processors provide last branch interrupt and
exception recording. This capability is almost identical to that found in Pentium 4 and
Intel Xeon processors. There are differences in the stack and in some MSR names
and locations.
Note the following:
exception recording. This capability is almost identical to that found in Pentium 4 and
Intel Xeon processors. There are differences in the stack and in some MSR names
and locations.
Note the following:
•
IA32_DEBUGCTL MSR — Enables debug trace interrupt, debug trace store,
trace messages enable, performance monitoring breakpoint flags, single
stepping on branches, and last branch. IA32_DEBUGCTL MSR is located at
register address 01D9H.
See Figure 16-14 for the layout and the entries below for a description of the
flags:
— LBR (last branch/interrupt/exception) flag (bit 0) — When set, the
trace messages enable, performance monitoring breakpoint flags, single
stepping on branches, and last branch. IA32_DEBUGCTL MSR is located at
register address 01D9H.
See Figure 16-14 for the layout and the entries below for a description of the
flags:
— LBR (last branch/interrupt/exception) flag (bit 0) — When set, the
processor records a running trace of the most recent branches, interrupts,
and/or exceptions taken by the processor (prior to a debug exception being
generated) in the last branch record (LBR) stack. For more information, see
the “Last Branch Record (LBR) Stack” below.
and/or exceptions taken by the processor (prior to a debug exception being
generated) in the last branch record (LBR) stack. For more information, see
the “Last Branch Record (LBR) Stack” below.
— BTF (single-step on branches) flag (bit 1) — When set, the processor
treats the TF flag in the EFLAGS register as a “single-step on branches” flag
rather than a “single-step on instructions” flag. This mechanism allows
single-stepping the processor on taken branches, interrupts, and exceptions.
See Section 16.4.3, “Single-Stepping on Branches, Exceptions, and Inter-
rupts,” for more information about the BTF flag.
rather than a “single-step on instructions” flag. This mechanism allows
single-stepping the processor on taken branches, interrupts, and exceptions.
See Section 16.4.3, “Single-Stepping on Branches, Exceptions, and Inter-
rupts,” for more information about the BTF flag.
— TR (trace message enable) flag (bit 6) — When set, branch trace
messages are enabled. When the processor detects a taken branch,
interrupt, or exception; it sends the branch record out on the system bus as
a branch trace message (BTM). See Section 16.4.4, “Branch Trace Messages,”
for more information about the TR flag.
interrupt, or exception; it sends the branch record out on the system bus as
a branch trace message (BTM). See Section 16.4.4, “Branch Trace Messages,”
for more information about the TR flag.
— BTS (branch trace store) flag (bit 7) — When set, the flag enables BTS
facilities to log BTMs to a memory-resident BTS buffer that is part of the DS
save area. See Section 16.4.9, “BTS and DS Save Area.”
save area. See Section 16.4.9, “BTS and DS Save Area.”
— BTINT (branch trace interrupt) flag (bits 8) — When set, the BTS
facilities generate an interrupt when the BTS buffer is full. When clear, BTMs are
logged to the BTS buffer in a circular fashion. See Section 16.4.5, “Branch Trace
Store (BTS),” for a description of this mechanism.
logged to the BTS buffer in a circular fashion. See Section 16.4.5, “Branch Trace
Store (BTS),” for a description of this mechanism.