Intel 253668-032US Benutzerhandbuch
17-22 Vol. 3
8086 EMULATION
executed must be 0, otherwise the processor does not change the state of the VM
flag.
flag.
17.3.2 Class
2—Maskable
Hardware Interrupt Handling in
Virtual-8086 Mode Using the Virtual Interrupt Mechanism
Maskable hardware interrupts are those interrupts that are delivered through the
INTR# pin or through an interrupt request to the local APIC (see Section 6.3.2,
“Maskable Hardware Interrupts”). These interrupts can be inhibited (masked) from
interrupting an executing program or task by clearing the IF flag in the EFLAGS
register.
When the VME flag in control register CR4 is set and the IOPL field in the EFLAGS
register is less than 3, two additional flags are activated in the EFLAGS register:
INTR# pin or through an interrupt request to the local APIC (see Section 6.3.2,
“Maskable Hardware Interrupts”). These interrupts can be inhibited (masked) from
interrupting an executing program or task by clearing the IF flag in the EFLAGS
register.
When the VME flag in control register CR4 is set and the IOPL field in the EFLAGS
register is less than 3, two additional flags are activated in the EFLAGS register:
•
VIF (virtual interrupt) flag, bit 19 of the EFLAGS register.
•
VIP (virtual interrupt pending) flag, bit 20 of the EFLAGS register.
These flags provide the virtual-8086 monitor with more efficient control over
handling maskable hardware interrupts that occur during virtual-8086 mode tasks.
They also reduce interrupt-handling overhead, by eliminating the need for all IF
related operations (such as PUSHF, POPF, CLI, and STI instructions) to trap to the
virtual-8086 monitor. The purpose and use of these flags are as follows.
handling maskable hardware interrupts that occur during virtual-8086 mode tasks.
They also reduce interrupt-handling overhead, by eliminating the need for all IF
related operations (such as PUSHF, POPF, CLI, and STI instructions) to trap to the
virtual-8086 monitor. The purpose and use of these flags are as follows.
NOTE
The VIF and VIP flags are only available in IA-32 processors that
support the virtual mode extensions. These extensions were
introduced in the IA-32 architecture with the Pentium processor.
When this mechanism is either not available or not enabled,
maskable hardware interrupts are handled as class 1 interrupts.
Here, if VIF and VIP flags are needed, the virtual-8086 monitor can
implement them in software.
support the virtual mode extensions. These extensions were
introduced in the IA-32 architecture with the Pentium processor.
When this mechanism is either not available or not enabled,
maskable hardware interrupts are handled as class 1 interrupts.
Here, if VIF and VIP flags are needed, the virtual-8086 monitor can
implement them in software.
Existing 8086 programs commonly set and clear the IF flag in the EFLAGS register to
enable and disable maskable hardware interrupts, respectively; for example, to
disable interrupts while handling another interrupt or an exception. This practice
works well in single task environments, but can cause problems in multitasking and
multiple-processor environments, where it is often desirable to prevent an applica-
tion program from having direct control over the handling of hardware interrupts.
When using earlier IA-32 processors, this problem was often solved by creating a
virtual IF flag in software. The IA-32 processors (beginning with the Pentium
processor) provide hardware support for this virtual IF flag through the VIF and VIP
flags.
The VIF flag is a virtualized version of the IF flag, which an application program
running from within a virtual-8086 task can used to control the handling of maskable
hardware interrupts. When the VIF flag is enabled, the CLI and STI instructions
operate on the VIF flag instead of the IF flag. When an 8086 program executes the
enable and disable maskable hardware interrupts, respectively; for example, to
disable interrupts while handling another interrupt or an exception. This practice
works well in single task environments, but can cause problems in multitasking and
multiple-processor environments, where it is often desirable to prevent an applica-
tion program from having direct control over the handling of hardware interrupts.
When using earlier IA-32 processors, this problem was often solved by creating a
virtual IF flag in software. The IA-32 processors (beginning with the Pentium
processor) provide hardware support for this virtual IF flag through the VIF and VIP
flags.
The VIF flag is a virtualized version of the IF flag, which an application program
running from within a virtual-8086 task can used to control the handling of maskable
hardware interrupts. When the VIF flag is enabled, the CLI and STI instructions
operate on the VIF flag instead of the IF flag. When an 8086 program executes the