Intel 253668-032US Benutzerhandbuch
Vol. 3 19-3
ARCHITECTURE COMPATIBILITY
original value results in a general-protection exception (#GP). So, programs that
execute on the P6 family and Pentium processors cannot erroneously enable func-
tions that may be implemented in future IA-32 processors.
The P6 family and Pentium processors do not check for attempts to set reserved bits
in model-specific registers; however these bits may be checked on more recent
processors. It is the obligation of the software writer to enforce this discipline. These
reserved bits may be used in future Intel processors.
execute on the P6 family and Pentium processors cannot erroneously enable func-
tions that may be implemented in future IA-32 processors.
The P6 family and Pentium processors do not check for attempts to set reserved bits
in model-specific registers; however these bits may be checked on more recent
processors. It is the obligation of the software writer to enforce this discipline. These
reserved bits may be used in future Intel processors.
19.4
DETECTING THE PRESENCE OF NEW FEATURES
THROUGH SOFTWARE
Software can check for the presence of new architectural features and extensions in
either of two ways:
1. Test for the presence of the feature or extension. Software can test for the
either of two ways:
1. Test for the presence of the feature or extension. Software can test for the
presence of new flags in the EFLAGS register and control registers. If these flags
are reserved (meaning not present in the processor executing the test), an
exception is generated. Likewise, software can attempt to execute a new
instruction, which results in an invalid-opcode exception (#UD) being generated
if it is not supported.
are reserved (meaning not present in the processor executing the test), an
exception is generated. Likewise, software can attempt to execute a new
instruction, which results in an invalid-opcode exception (#UD) being generated
if it is not supported.
2. Execute the CPUID instruction. The CPUID instruction (added to the IA-32 in the
Pentium processor) indicates the presence of new features directly.
See Chapter 14, “Processor Identification and Feature Determination,” in the Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for detailed
information on detecting new processor features and extensions.
64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for detailed
information on detecting new processor features and extensions.
19.5 INTEL
MMX
TECHNOLOGY
The Pentium processor with MMX technology introduced the MMX technology and a
set of MMX instructions to the IA-32. The MMX instructions are described in Chapter
9, “Programming with Intel® MMX™ Technology,” in the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 1, and in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volumes 2A & 2B. The MMX technology
and MMX instructions are also included in the Pentium II, Pentium III, Pentium 4, and
Intel Xeon processors.
set of MMX instructions to the IA-32. The MMX instructions are described in Chapter
9, “Programming with Intel® MMX™ Technology,” in the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 1, and in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volumes 2A & 2B. The MMX technology
and MMX instructions are also included in the Pentium II, Pentium III, Pentium 4, and
Intel Xeon processors.
19.6
STREAMING SIMD EXTENSIONS (SSE)
The Streaming SIMD Extensions (SSE) were introduced in the Pentium III processor.
The SSE extensions consist of a new set of instructions and a new set of registers.
The new registers include the eight 128-bit XMM registers and the 32-bit MXCSR
The SSE extensions consist of a new set of instructions and a new set of registers.
The new registers include the eight 128-bit XMM registers and the 32-bit MXCSR