Intel 253668-032US Benutzerhandbuch
19-16 Vol. 3
ARCHITECTURE COMPATIBILITY
19.18.6.9 Alignment Check Exceptions (#AC)
If alignment checking is enabled, a misaligned data operand on the P6 family,
Pentium, and Intel486 processors causes an alignment check exception (#AC) when
a program or procedure is running at privilege-level 3, except for the stack portion of
the FSAVE/FNSAVE, FXSAVE, FRSTOR, and FXRSTOR instructions.
Pentium, and Intel486 processors causes an alignment check exception (#AC) when
a program or procedure is running at privilege-level 3, except for the stack portion of
the FSAVE/FNSAVE, FXSAVE, FRSTOR, and FXRSTOR instructions.
19.18.6.10 Segment Not Present Exception During FLDENV
On the Intel486 processor, when a segment not present exception (#NP) occurs in
the middle of an FLDENV instruction, it can happen that part of the environment is
loaded and part not. In such cases, the FPU control word is left with a value of 007FH.
The P6 family and Pentium processors ensure the internal state is correct at all times
by attempting to read the first and last bytes of the environment before updating the
internal state.
the middle of an FLDENV instruction, it can happen that part of the environment is
loaded and part not. In such cases, the FPU control word is left with a value of 007FH.
The P6 family and Pentium processors ensure the internal state is correct at all times
by attempting to read the first and last bytes of the environment before updating the
internal state.
19.18.6.11 Device Not Available Exception (#NM)
The device-not-available exception (#NM, interrupt 7) will occur in the P6 family,
Pentium, and Intel486 processors as described in Section 2.5, “Control Registers,”
Table 2-1, and Chapter 6, “Interrupt 7—Device Not Available Exception (#NM).”
Pentium, and Intel486 processors as described in Section 2.5, “Control Registers,”
Table 2-1, and Chapter 6, “Interrupt 7—Device Not Available Exception (#NM).”
19.18.6.12 Coprocessor Segment Overrun Exception
The coprocessor segment overrun exception (interrupt 9) does not occur in the P6
family, Pentium, and Intel486 processors. In situations where the Intel 387 math
coprocessor would cause an interrupt 9, the P6 family, Pentium, and Intel486 proces-
sors simply abort the instruction. To avoid undetected segment overruns, it is recom-
mended that the floating-point save area be placed in the same page as the TSS. This
placement will prevent the FPU environment from being lost if a page fault occurs
during the execution of an FLDENV, FRSTOR, or FXRSTOR instruction while the oper-
ating system is performing a task switch.
family, Pentium, and Intel486 processors. In situations where the Intel 387 math
coprocessor would cause an interrupt 9, the P6 family, Pentium, and Intel486 proces-
sors simply abort the instruction. To avoid undetected segment overruns, it is recom-
mended that the floating-point save area be placed in the same page as the TSS. This
placement will prevent the FPU environment from being lost if a page fault occurs
during the execution of an FLDENV, FRSTOR, or FXRSTOR instruction while the oper-
ating system is performing a task switch.
19.18.6.13 General Protection Exception (#GP)
A general-protection exception (#GP, interrupt 13) occurs if the starting address of a
floating-point operand falls outside a segment’s size. An exception handler should be
included to report these programming errors.
floating-point operand falls outside a segment’s size. An exception handler should be
included to report these programming errors.
19.18.6.14 Floating-Point Error Exception (#MF)
In real mode and protected mode (not including virtual-8086 mode), interrupt vector
16 must point to the floating-point exception handler. In virtual 8086 mode, the
virtual-8086 monitor can be programmed to accommodate a different location of the
interrupt vector for floating-point exceptions.
16 must point to the floating-point exception handler. In virtual 8086 mode, the
virtual-8086 monitor can be programmed to accommodate a different location of the
interrupt vector for floating-point exceptions.