Intel 253668-032US Benutzerhandbuch
19-28 Vol. 3
ARCHITECTURE COMPATIBILITY
are enabled (the DE flag is set), attempts to reference registers DR4 or DR5 will
result in an invalid-opcode exception (#UD).
result in an invalid-opcode exception (#UD).
19.24 RECOGNITION OF BREAKPOINTS
For the Pentium processor, it is recommended that debuggers execute the LGDT
instruction before returning to the program being debugged to ensure that break-
points are detected. This operation does not need to be performed on the P6 family,
Intel486, or Intel386 processors.
The implementation of test registers on the Intel486 processor used for testing the
cache and TLB has been redesigned using MSRs on the P6 family and Pentium
processors. (Note that MSRs used for this function are different on the P6 family and
Pentium processors.) The MOV to and from test register instructions generate
invalid-opcode exceptions (#UD) on the P6 family processors.
instruction before returning to the program being debugged to ensure that break-
points are detected. This operation does not need to be performed on the P6 family,
Intel486, or Intel386 processors.
The implementation of test registers on the Intel486 processor used for testing the
cache and TLB has been redesigned using MSRs on the P6 family and Pentium
processors. (Note that MSRs used for this function are different on the P6 family and
Pentium processors.) The MOV to and from test register instructions generate
invalid-opcode exceptions (#UD) on the P6 family processors.
19.25 EXCEPTIONS AND/OR EXCEPTION CONDITIONS
This section describes the new exceptions and exception conditions added to the 32-
bit IA-32 processors and implementation differences in existing exception handling.
See Chapter 6, “Interrupt and Exception Handling,” for a detailed description of the
IA-32 exceptions.
The Pentium III processor introduced new state with the XMM registers. Computations
involving data in these registers can produce exceptions. A new MXCSR
control/status register is used to determine which exception or exceptions have
occurred. When an exception associated with the XMM registers occurs, an interrupt
is generated.
bit IA-32 processors and implementation differences in existing exception handling.
See Chapter 6, “Interrupt and Exception Handling,” for a detailed description of the
IA-32 exceptions.
The Pentium III processor introduced new state with the XMM registers. Computations
involving data in these registers can produce exceptions. A new MXCSR
control/status register is used to determine which exception or exceptions have
occurred. When an exception associated with the XMM registers occurs, an interrupt
is generated.
•
SIMD floating-point exception (#XF, interrupt 19) — New exceptions associated
with the SIMD floating-point registers and resulting computations.
with the SIMD floating-point registers and resulting computations.
No new exceptions were added with the Pentium Pro and Pentium II processors. The
set of available exceptions is the same as for the Pentium processor. However, the
following exception condition was added to the IA-32 with the Pentium Pro
processor:
set of available exceptions is the same as for the Pentium processor. However, the
following exception condition was added to the IA-32 with the Pentium Pro
processor:
•
Machine-check exception (#MC, interrupt 18) — New exception conditions. Many
exception conditions have been added to the machine-check exception and a new
architecture has been added for handling and reporting on hardware errors. See
Chapter 15, “Machine-Check Architecture,” for a detailed description of the new
conditions.
exception conditions have been added to the machine-check exception and a new
architecture has been added for handling and reporting on hardware errors. See
Chapter 15, “Machine-Check Architecture,” for a detailed description of the new
conditions.
The following exceptions and/or exception conditions were added to the IA-32 with
the Pentium processor:
the Pentium processor:
•
Machine-check exception (#MC, interrupt 18) — New exception. This exception
reports parity and other hardware errors. It is a model-specific exception and
reports parity and other hardware errors. It is a model-specific exception and