Intel 253668-032US Benutzerhandbuch
19-36 Vol. 3
ARCHITECTURE COMPATIBILITY
19.29.2 Disabling the L3 Cache
A unified third-level (L3) cache in processors based on Intel NetBurst microarchitec-
ture (see Section 11.1, “Internal Caches, TLBs, and Buffers”) provides the third-level
cache disable flag, bit 6 of the IA32_MISC_ENABLE MSR. The third-level cache
disable flag allows the L3 cache to be disabled and enabled, independently of the L1
and L2 caches (see Section 11.5.4, “Disabling and Enabling the L3 Cache”). The
third-level cache disable flag applies only to processors based on Intel NetBurst
microarchitecture. Processors with L3 and based on other microarchitectures do not
support the third-level cache disable flag.
ture (see Section 11.1, “Internal Caches, TLBs, and Buffers”) provides the third-level
cache disable flag, bit 6 of the IA32_MISC_ENABLE MSR. The third-level cache
disable flag allows the L3 cache to be disabled and enabled, independently of the L1
and L2 caches (see Section 11.5.4, “Disabling and Enabling the L3 Cache”). The
third-level cache disable flag applies only to processors based on Intel NetBurst
microarchitecture. Processors with L3 and based on other microarchitectures do not
support the third-level cache disable flag.
19.30 PAGING
This section identifies enhancements made to the paging mechanism and implemen-
tation differences in the paging mechanism for various IA-32 processors.
tation differences in the paging mechanism for various IA-32 processors.
19.30.1 Large
Pages
The Pentium processor extended the memory management/paging facilities of the
IA-32 to allow large (4 MBytes) pages sizes (see Section 4.3, “32-Bit Paging”). The
first P6 family processor (the Pentium Pro processor) added a 2 MByte page size to
the IA-32 in conjunction with the physical address extension (PAE) feature (see
Section 4.4, “PAE Paging”).
The availability of large pages with 32-bit paging on any IA-32 processor can be
determined via feature bit 3 (PSE) of register EDX after the CPUID instruction has
been execution with an argument of 1. (Large pages are always available with PAE
paging and IA-32e paging.) Intel processors that do not support the CPUID instruc-
tion support only 32-bit paging and do not support page size enhancements. (See
“CPUID—CPU Identification” in Chapter 3, “Instruction Set Reference, A-M,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, and AP-
485, Intel Processor Identification and the CPUID Instruction, for more information
on the CPUID instruction.)
IA-32 to allow large (4 MBytes) pages sizes (see Section 4.3, “32-Bit Paging”). The
first P6 family processor (the Pentium Pro processor) added a 2 MByte page size to
the IA-32 in conjunction with the physical address extension (PAE) feature (see
Section 4.4, “PAE Paging”).
The availability of large pages with 32-bit paging on any IA-32 processor can be
determined via feature bit 3 (PSE) of register EDX after the CPUID instruction has
been execution with an argument of 1. (Large pages are always available with PAE
paging and IA-32e paging.) Intel processors that do not support the CPUID instruc-
tion support only 32-bit paging and do not support page size enhancements. (See
“CPUID—CPU Identification” in Chapter 3, “Instruction Set Reference, A-M,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, and AP-
485, Intel Processor Identification and the CPUID Instruction, for more information
on the CPUID instruction.)
19.30.2 PCD and PWT Flags
The PCD and PWT flags were introduced to the IA-32 in the Intel486 processor to
control the caching of pages:
control the caching of pages:
•
PCD (page-level cache disable) flag—Controls caching on a page-by-page basis.
•
PWT (page-level write-through) flag—Controls the write-through/writeback
caching policy on a page-by-page basis. Since the internal cache of the Intel486
processor is a write-through cache, it is not affected by the state of the PWT flag.
caching policy on a page-by-page basis. Since the internal cache of the Intel486
processor is a write-through cache, it is not affected by the state of the PWT flag.