Intel 253668-032US Benutzerhandbuch
Vol. 3 19-39
ARCHITECTURE COMPATIBILITY
19.32 MIXING 16- AND 32-BIT SEGMENTS
The features of the 16-bit Intel 286 processor are an object-code compatible subset
of those of the 32-bit IA-32 processors. The D (default operation size) flag in
segment descriptors indicates whether the processor treats a code or data segment
as a 16-bit or 32-bit segment; the B (default stack size) flag in segment descriptors
indicates whether the processor treats a stack segment as a 16-bit or 32-bit
segment.
The segment descriptors used by the Intel 286 processor are supported by the 32-bit
IA-32 processors if the Intel-reserved word (highest word) of the descriptor is clear.
On the 32-bit IA-32 processors, this word includes the upper bits of the base address
and the segment limit.
The segment descriptors for data segments, code segments, local descriptor tables
(there are no descriptors for global descriptor tables), and task gates are the same
for the 16- and 32-bit processors. Other 16-bit descriptors (TSS segment, call gate,
interrupt gate, and trap gate) are supported by the 32-bit processors.
The 32-bit processors also have descriptors for TSS segments, call gates, interrupt
gates, and trap gates that support the 32-bit architecture. Both kinds of descriptors
can be used in the same system.
For those segment descriptors common to both 16- and 32-bit processors, clear bits
in the reserved word cause the 32-bit processors to interpret these descriptors
exactly as an Intel 286 processor does, that is:
of those of the 32-bit IA-32 processors. The D (default operation size) flag in
segment descriptors indicates whether the processor treats a code or data segment
as a 16-bit or 32-bit segment; the B (default stack size) flag in segment descriptors
indicates whether the processor treats a stack segment as a 16-bit or 32-bit
segment.
The segment descriptors used by the Intel 286 processor are supported by the 32-bit
IA-32 processors if the Intel-reserved word (highest word) of the descriptor is clear.
On the 32-bit IA-32 processors, this word includes the upper bits of the base address
and the segment limit.
The segment descriptors for data segments, code segments, local descriptor tables
(there are no descriptors for global descriptor tables), and task gates are the same
for the 16- and 32-bit processors. Other 16-bit descriptors (TSS segment, call gate,
interrupt gate, and trap gate) are supported by the 32-bit processors.
The 32-bit processors also have descriptors for TSS segments, call gates, interrupt
gates, and trap gates that support the 32-bit architecture. Both kinds of descriptors
can be used in the same system.
For those segment descriptors common to both 16- and 32-bit processors, clear bits
in the reserved word cause the 32-bit processors to interpret these descriptors
exactly as an Intel 286 processor does, that is:
•
Base Address — The upper 8 bits of the 32-bit base address are clear, which limits
base addresses to 24 bits.
base addresses to 24 bits.
•
Limit — The upper 4 bits of the limit field are clear, restricting the value of the
limit field to 64 KBytes.
limit field to 64 KBytes.
•
Granularity bit — The G (granularity) flag is clear, indicating the value of the
16-bit limit is interpreted in units of 1 byte.
16-bit limit is interpreted in units of 1 byte.
•
Big bit — In a data-segment descriptor, the B flag is clear in the segment
descriptor used by the 32-bit processors, indicating the segment is no larger than
64 KBytes.
descriptor used by the 32-bit processors, indicating the segment is no larger than
64 KBytes.
•
Default bit — In a code-segment descriptor, the D flag is clear, indicating 16-bit
addressing and operands are the default. In a stack-segment descriptor, the D
flag is clear, indicating use of the SP register (instead of the ESP register) and a
64-KByte maximum segment limit.
addressing and operands are the default. In a stack-segment descriptor, the D
flag is clear, indicating use of the SP register (instead of the ESP register) and a
64-KByte maximum segment limit.
For information on mixing 16- and 32-bit code in applications, see Chapter 18,
“Mixing 16-Bit and 32-Bit Code.”
“Mixing 16-Bit and 32-Bit Code.”
19.33 SEGMENT AND ADDRESS WRAPAROUND
This section discusses differences in segment and address wraparound between the
P6 family, Pentium, Intel486, Intel386, Intel 286, and 8086 processors.
P6 family, Pentium, Intel486, Intel386, Intel 286, and 8086 processors.