Intel 253668-032US Benutzerhandbuch
Vol. 3 2-29
SYSTEM ARCHITECTURE OVERVIEW
2.7.1
Loading and Storing System Registers
The GDTR, LDTR, IDTR, and TR registers each have a load and store instruction for
loading data into and storing data from the register:
loading data into and storing data from the register:
•
LGDT (Load GDTR Register) — Loads the GDT base address and limit from
memory into the GDTR register.
memory into the GDTR register.
•
SGDT (Store GDTR Register) — Stores the GDT base address and limit from
the GDTR register into memory.
the GDTR register into memory.
•
LIDT (Load IDTR Register) — Loads the IDT base address and limit from
memory into the IDTR register.
memory into the IDTR register.
•
SIDT (Load IDTR Register — Stores the IDT base address and limit from the
IDTR register into memory.
IDTR register into memory.
•
LLDT (Load LDT Register) — Loads the LDT segment selector and segment
descriptor from memory into the LDTR. (The segment selector operand can also
be located in a general-purpose register.)
descriptor from memory into the LDTR. (The segment selector operand can also
be located in a general-purpose register.)
•
SLDT (Store LDT Register) — Stores the LDT segment selector from the LDTR
register into memory or a general-purpose register.
register into memory or a general-purpose register.
•
LTR (Load Task Register) — Loads segment selector and segment descriptor
for a TSS from memory into the task register. (The segment selector operand can
also be located in a general-purpose register.)
for a TSS from memory into the task register. (The segment selector operand can
also be located in a general-purpose register.)
•
STR (Store Task Register) — Stores the segment selector for the current task
TSS from the task register into memory or a general-purpose register.
TSS from the task register into memory or a general-purpose register.
XGETBV
Return the state of the the
XFEATURE_ENABLED_MASK register
Yes
No
XSETBV
Enable one or more processor
extended states
No
6
Yes
NOTES:
1. Useful to application programs running at a CPL of 1 or 2.
2. The TSD and PCE flags in control register CR4 control access to these instructions by application
2. The TSD and PCE flags in control register CR4 control access to these instructions by application
programs running at a CPL of 3.
3. These instructions were introduced into the IA-32 Architecture with the Pentium processor.
4. This instruction was introduced into the IA-32 Architecture with the Pentium Pro processor and
4. This instruction was introduced into the IA-32 Architecture with the Pentium Pro processor and
the Pentium processor with MMX technology.
5. This instruction is not supported in 64-bit mode.
6. Application uses XGETBV to query which set of processor extended states are enabled.
7. RDTSCP is introduced in Intel Core i7 processor.
6. Application uses XGETBV to query which set of processor extended states are enabled.
7. RDTSCP is introduced in Intel Core i7 processor.
Table 2-2. Summary of System Instructions (Contd.)
Instruction
Description
Useful to
Application?
Protected from
Application?