Intel SE7501WV2 Benutzerhandbuch
BIOS
Intel® Server Board SE7501WV2 TPS
Revision
1.0
Intel reference number C25653-001
76
6.5.3 PCI
Auto-Configuration
The system BIOS supports the INT 1Ah, AH = B1h functions, in conformance with the PCI Local
Bus Specification, Revision 2.1. The system BIOS also supports the 16- and 32-bit protected
mode interfaces as required by the PCI BIOS Specification, Revision 2.1.
Bus Specification, Revision 2.1. The system BIOS also supports the 16- and 32-bit protected
mode interfaces as required by the PCI BIOS Specification, Revision 2.1.
Beginning at the lowest device, the BIOS uses a “depth-first” scan algorithm to enumerate the
PCI buses. Each time a bridge device is located, the bus number is incremented and scanning
continues on the secondary side of the bridge until all devices on the current bus are scanned.
PCI buses. Each time a bridge device is located, the bus number is incremented and scanning
continues on the secondary side of the bridge until all devices on the current bus are scanned.
The BIOS then scans for PCI devices using a “breadth-first” search. All devices on a given bus
are scanned from lowest to highest before the next bus number is scanned.
are scanned from lowest to highest before the next bus number is scanned.
The system BIOS POST maps each device into memory and/or I/O space, and assigns IRQ
channels as required. The BIOS programs the PCI-ISA interrupt routing logic in the chipset
hardware to steer PCI interrupts to compatible ISA IRQs.
channels as required. The BIOS programs the PCI-ISA interrupt routing logic in the chipset
hardware to steer PCI interrupts to compatible ISA IRQs.
The BIOS dispatches any option ROM code for PCI devices to the DOS compatibility hole
(C0000h to E7FFFh) and transfers control to the entry point. Because the DOS compatibility
hole is a limited resource, system configurations with a large number of PCI devices may
encounter a shortage of this resource. If the BIOS runs out of option ROM space, some PCI
option ROMs are not executed and a POST error is generated. The scanning of PCI option
ROMs can be controlled on a slot-by-slot basis in BIOS setup.
(C0000h to E7FFFh) and transfers control to the entry point. Because the DOS compatibility
hole is a limited resource, system configurations with a large number of PCI devices may
encounter a shortage of this resource. If the BIOS runs out of option ROM space, some PCI
option ROMs are not executed and a POST error is generated. The scanning of PCI option
ROMs can be controlled on a slot-by-slot basis in BIOS setup.
Drivers and/or the operating system can detect installed devices and determine resource
consumption using the defined PCI, legacy PnP BIOS, and/or ACPI BIOS interface functions.
consumption using the defined PCI, legacy PnP BIOS, and/or ACPI BIOS interface functions.
6.6 NVRAM
API
The non-volatile RAM (NVRAM) API and the PCI data records are not supported by the system
BIOS. The configuration information of the PCI devices is stored in ESCD. The System Setup
Utility can update the ESCD to change the IRQ assigned to a PCI device.
BIOS. The configuration information of the PCI devices is stored in ESCD. The System Setup
Utility can update the ESCD to change the IRQ assigned to a PCI device.
6.7 Legacy ISA Configuration
Legacy ISA add-in devices are not supported.
6.8 Automatic Detection of Video Adapters
The BIOS detects video adapters in the following order:
1. Off-board PCI
2. On-board PCI
The on-board (or off-board) video BIOS is shadowed, starting at address C0000h, and is
initialized before memory tests begin in POST. Precedence is always given to off-board devices.
initialized before memory tests begin in POST. Precedence is always given to off-board devices.