Renesas SH7264 Benutzerhandbuch
Section 17 I
2
C Bus Interface 3
Page 872 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
TDRE
TEND
ICDRS
ICDRR
1
A
2
1
3
4
5
6
7
8
9
9
A
TRS
RDRF
[1] Clear TDRE after clearing
TEND and TRS
TEND and TRS
[2] Read ICDRR (dummy read)
[3] Read ICDRR
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
Bit 7
Master transmit mode
Master receive mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User
processing
Data 1
Data 1
Figure 17.7 Master Receive Mode Operation Timing (1)
RDRF
RCVD
ICDRS
ICDRR
1
9
2
3
4
5
6
7
8
9
A
A/
A
Data n-1
Data n
Data n
Data n-1
[5] Read ICDRR after setting RCVD
[6] Issue stop
condition
condition
[7] Read ICDRR,
and clear RCVD
and clear RCVD
[8] Set slave
receive mode
receive mode
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User
processing
Figure 17.8 Master Receive Mode Operation Timing (2)