Renesas R5S72625 Benutzerhandbuch

 
Section 26   USB 2.0 Host/Function Module 

Page 1378 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

14 BCLR 

0 

R/W*

1

CPU Buffer Clear 

This bit should be set to 1 to clear the FIFO buffer on 
the CPU side for the selected pipe.  

0: Invalid  

1: Clears the buffer memory on the CPU side. 

When double buffer mode is set for the FIFO buffer 
assigned to the selected pipe, this module clears 
only one plane of the FIFO buffer even when both 
planes are read-enabled. 

When the selected pipe is the DCP, setting BCLR to 
1 allows this module to clear the FIFO buffer 
regardless of whether the FIFO buffer is on the CPU 
side or SIE side. To clear the buffer on the SIE side, 
set the PID bits for the DCP to NAK before setting 
BCLR to 1. 

When the selected pipe is not the DCP, writing 1 to 
this bit should be done while FRDY indicates 1 (set 
by this module). 

13 

FRDY 

0 

R 

FIFO Port Ready 

Indicates whether the FIFO port can be accessed. 

0: FIFO port access is disabled. 

1: FIFO port access is enabled. 

In the following cases, this module sets FRDY to 1 
but data cannot be read via the FIFO port because 
there is no data to be read. In these cases, set BCLR 
to 1 to clear the FIFO buffer, and enable 
transmission and reception of the next data. 

  A zero-length packet is received when the FIFO 

buffer assigned to the selected pipe is empty. 

  A short packet is received and the data is 

completely read while BFRE is 1.