Renesas R5S72623 Benutzerhandbuch
Section 7 Interrupt Controller
Page 196 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Item
Number of States
Remarks
NMI
User Debugging
Interface
IRQ, PINT
USB 2.0 host/
function module
Peripheral
Module (Other
than USB 2.0
host/
function
module)
Interrupt
response
time
No
register
banking
Min. 5
Icyc
2 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc
1 Pcyc +
m1 + m2
5 Icyc
3 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc
4 Bcyc +
m1 + m2
5 Icyc
2 Bcyc +
m1 + m2
144-MHz operation*
1
*
2
:
0.076 to 0.118
s
Max. 6 Icyc
2 Bcyc +
1 Pcyc +
2(m1 + m2) + m3
6 Icyc
1 Pcyc +
2(m1 + m2) + m3
6 Icyc
3 Bcyc +
1 Pcyc +
2(m1 + m2) + m3
6 Icyc
4 Bcyc +
2(m1 + m2) + m3
6 Icyc
2 Bcyc +
2(m1 + m2) + m3
144-MHz operation*
1
*
2
:
0.104 to 0.145
s
Register
banking
without
register
bank
overflow
Min.
5
Icyc
1 Pcyc +
m1 + m2
5 Icyc
3 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc
4 Bcyc +
m1 + m2
5 Icyc
2 Bcyc +
m1 + m2
144-MHz operation*
1
*
2
:
0.076 to 0.118
s
Max.
14
Icyc
1 Pcyc +
m1 + m2
14 Icyc
3 Bcyc +
1 Pcyc +
m1 + m2
14 Icyc
4 Bcyc +
m1 + m2
14 Icyc
2 Bcyc +
m1 + m2
144-MHz operation*
1
*
2
:
0.138 to 0.180
s
Register
banking
with
register
bank
overflow
Min.
5
Icyc
1 Pcyc +
m1 + m2
5 Icyc
3 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc
4 Bcyc +
m1 + m2
5 Icyc
2 Bcyc +
m1 + m2
144-MHz operation*
1
*
2
:
0.076 to 0.118
s
Max.
5
Icyc
1 Pcyc + m1 +
m2 + 19(m4)
5 Icyc
3 Bcyc +
1 Pcyc + m1 +
m2 + 19(m4)
5 Icyc
4 Bcyc +
m1 + m2 +
19(m4)
5 Icyc
2 Bcyc +
m1 + m2 +
19(m4)
144-MHz operation*
1
*
2
:
0.208 to 0.250
s
Notes: m1 to m4 are the number of states needed for the following memory accesses.
m1: Vector address read (longword read)
m2: SR save (longword write)
m3: PC save (longword write)
m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the
stack.
stack.
1. In the case that m1 = m2 = m3 = m4 = 1 Icyc.
2. In the case that (I
, B, P) = (144 MHz, 72 MHz, 36 MHz).