Renesas R5S72621 Benutzerhandbuch
Section 2 CPU
R01UH0134EJ0400 Rev. 4.00
Page 61 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Addressing
Mode
Mode
Instruction
Format
Format
Effective Address Calculation
Equation
Register indirect
with
displacement
with
displacement
@(disp:4,
Rn)
The effective address is the sum of Rn and a 4-bit
displacement (disp). The value of disp is zero-
extended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
displacement (disp). The value of disp is zero-
extended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
Rn
Rn + disp
× 1/2/4
+
×
1/2/4
disp
(zero-extended)
Byte:
Rn + disp
Rn + disp
Word:
Rn + disp
Rn + disp
2
Longword:
Rn + disp
Rn + disp
4
Register indirect
with
displacement
with
displacement
@(disp:12,
Rn)
The effective address is the sum of Rn and a 12-
bit
displacement (disp). The value of disp is zero-
extended.
bit
displacement (disp). The value of disp is zero-
extended.
+
Rn
disp
(zero-extended)
Rn + disp
Byte:
Rn + disp
Rn + disp
Word:
Rn + disp
Rn + disp
Longword:
Rn + disp
Rn + disp
Indexed register
indirect
indirect
@(R0,Rn)
The effective address is the sum of Rn and R0.
Rn
R0
Rn + R0
+
Rn + R0
GBR indirect
with
displacement
with
displacement
@(disp:8,
GBR)
The effective address is the sum of GBR value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and remains unchanged for
a byte operation, is doubled for a word operation,
and is quadrupled for a longword operation.
and an 8-bit displacement (disp). The value of
disp is zero-extended, and remains unchanged for
a byte operation, is doubled for a word operation,
and is quadrupled for a longword operation.
GBR
1/2/4
GBR
+ disp
× 1/2/4
+
×
disp
(zero-extended)
Byte:
GBR + disp
GBR + disp
Word:
GBR + disp
GBR + disp
2
Longword:
GBR + disp
GBR + disp
4