Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Datenbogen

Datasheet

113

B/D/F/Type:

0/0/0/MCHBAR

Address Offset: 29C–29Fh

Default Value:

00000000h

Access:

RO, RW 

Size:

32 bits

This register provides ODT controls. 

B/D/F/Type:

0/0/0/MCHBAR

Address Offset: 600–601h

Default Value:

0000h

Access:

RW/L, RO 

Size:

16 bits

The operation of this register is detailed in the description for the C0DRB0 register. 

31:12

RO

00000h Reserved 

11:8

RW

0h

DRAM ODT for Read Commands (sd0_cr_odt_duration_rd): Specifies the 
duration in MDCLKs to assert DRAM ODT for Read Commands. The Async value 
should be used when the Dynamic Powerdown bit is set. Else use the Sync value.

7:4

RW

0h

DRAM ODT for Write Commands (sd0_cr_odt_duration_wr): Specifies the 
duration in MDCLKs to assert DRAM ODT for Write Commands. The Async value 
should be used when the Dynamic Powerdown bit is set. Else use the Sync value.

3:0

RW

0h

MCH ODT for Read Commands (sd0_cr_mchodt_duration): Specifies the 
duration in MDCLKs to assert MCH ODT for Read Commands

15:10

RO

000000b Reserved

9:0

RW/L

000h

Channel 1 DRAM Rank Boundary Address 0 (C1DRBA0): See C0DRB0 
register.
In stacked mode, if this is the topmost populated rank in Channel 1, program 
this value to be cumulative of Ch0 DRB3.
This register is locked by ME stolen Memory lock.