Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Datenbogen
Produktcode
P4X-UPE3210-316-6M1333
Datasheet
215
Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel
®
3210 MCH only)
8.1
VID1—Vendor Identification
B/D/F/Type:
0/6/0/PCI
Address Offset: 0–1h
Default Value:
8086h
Access:
RO
Size:
16 bits
This register combined with the Device Identification register uniquely identify any PCI
device.
EC–EFh
PELC
PCI Express Legacy Control
00000000h
RO, RW
100–103h
VCECH
Virtual Channel Enhanced Capability
Header
Header
14010002h
RO
104–107h
PVCCAP1
Port VC Capability Register 1
00000000h
RO
108–10Bh
PVCCAP2
Port VC Capability Register 2
00000000h
RO
10C–10Dh
PVCCTL
Port VC Control
0000h
RO, RW
110–113h
VC0RCAP
VC0 Resource Capability
00000000h
RO
114–117h
VC0RCTL
VC0 Resource Control
800000FFh
RO, RW
11A–11Bh
VC0RSTS
VC0 Resource Status
0002h
RO
140–143h
RCLDECH
Root Complex Link Declaration Enhanced
00010005h
RO
144–147h
ESD
Element Self Description
03000100h
RO, RWO
150–153h
LE1D
Link Entry 1 Description
00000000h
RO, RWO
158–15Fh
LE1A
Link Entry 1 Address
0000000000
000000h
RO, RWO
Table 15.
Host-Secondary PCI Express* Bridge Register Address Map (D6:F0) (Sheet 3
of 3)
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
Bit
Access
Default
Value
Description
15:0
RO
8086h
Vendor Identification (VID1): PCI standard identification for Intel.