Renesas R5S72647 Benutzerhandbuch

 

Section 26   USB 2.0 Host/Function Module 

R01UH0134EJ0400  Rev. 4.00  

 

Page 1465 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

9 

TRENB 

0 

R/W 

Transaction Counter Enable 

Enables or disables the transaction counter. 

0: The transaction counter is disabled. 

1: The transaction counter is enabled. 

For the pipe in the receiving direction, setting this bit 
to 1 after setting the total number of the packets to 
be received in the TRNCNT bits allows this module 
to control hardware as described below on having 
received the number of packets equal to the set 
value in the TRNCNT bits. 

  In continuous transmission/reception mode 

(CNTMD = 1), this module switches the FIFO 

buffer to the CPU side even if the FIFO buffer is 

not full on completion of reception. 

  While SHTNAK is 1, this module modifies the PID 

bits to NAK for the corresponding pipe on having 

received the number of packets equal to the set 

value in the TRNCNT bits.  

  While BFRE is 1, this module asserts the BRDY 

interrupt on having received the number of 

packets equal to the set value in the TRNCNT 

bits and then reading out the last received data.  

For the pipe in the transmitting direction, set this bit 
to 0. 

When the transaction counter is not used, set this bit 
to 0. 

When the transaction counter is used, set the 
TRNCNT bits before setting this bit to 1. Set this bit 
to 1 before receiving the first packet to be counted by 
the transaction counter.  

8 TRCLR  0 R/W*

1

Transaction Counter Clear 

Clears the current value of the transaction counter 
corresponding to the pertinent pipe and then sets this 
bit to 0. 

0: Invalid 

1: The current counter value is cleared.