Renesas R5S72645 Benutzerhandbuch
Section 32 General Purpose I/O Ports
Page 1746 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
(8) Port G Control Register 0 (PGCR0)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R/W
R/W
R
R
R/W
R/W
R
R
R/W
R/W
R
R
R
R
-
PG2MD[1:0]
PG1MD[1:0]
PG3MD[1:0]
-
-
-
-
-
-
-
-
-
Bit:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W
Description
15, 14
All
0
R
Reserved
These bits are always read as 0. The write
value should always be 0.
value should always be 0.
13, 12
PG3MD[1:0] 00 R/W
PG3
Mode
Select the function of the PG3.
00: PG3
01: LCD_DATA3
10: SD_CLK
11: PINT3
11, 10
All
0
R
Reserved
These bits are always read as 0. The write
value should always be 0.
value should always be 0.
9, 8
PG2MD[1:0] 00 R/W
PG2
Mode
Select the function of the PG2.
00: PG2
01: LCD_DATA2
10: SD_CMD
11: PINT2
7, 6
All
0
R
Reserved
These bits are always read as 0. The write
value should always be 0.
value should always be 0.
5, 4
PG1MD[1:0] 00 R/W
PG1
Mode
Select the function of the PG1.
00: PG1
01: LCD_DATA1
10: SD_D3
11: PINT1
3 to 0
All
0
R
Reserved
These bits are always read as 0. The write
value should always be 0.
value should always be 0.