Renesas R5S72645 Benutzerhandbuch
Section 19 Serial I/O with FIFO
R01UH0134EJ0400 Rev. 4.00
Page 947 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
1 TXRST
0 R/W
Transmit
Reset
0: Does not reset transmit operation
1: Resets transmit operation
This bit setting becomes valid immediately. This bit
should be cleared to 0 before setting the register to
be initialized.
When the 1 setting for this bit becomes valid, this
module immediately sets the SIOFTxD pin output to
1, and initializes the following registers and data:
SITDR
Valid data in transmit FIFO
The TFEMP and TDREQ bits in SISTR
The TXE bit
SITDR
Valid data in transmit FIFO
The TFEMP and TDREQ bits in SISTR
The TXE bit
Note:
Set this bit to 1 for more than one transfer
clock period.
clock period.
0 RXRST
0 R/W
Receive
Reset
0: Does not reset receive operation
1: Resets receive operation
This bit setting becomes valid immediately. This bit
should be cleared to 0 before setting the register to
be initialized.
When the 1 setting for this bit becomes valid, this
module immediately disables reception from the
SIOFRxD pin, and initializes the following registers
and data:
SIRDR
Valid data in receive FIFO
The RFFUL and RDREQ bits in SISTR
The RXE bit
SIRDR
Valid data in receive FIFO
The RFFUL and RDREQ bits in SISTR
The RXE bit
Note:
Set this bit to 1 for more than one transfer
clock period.
clock period.