Enterasys 9500 Installationsanweisungen
3-3
ATM Cell Traffic Flow in the 9A686-04
SARI (Segmentation and Reassembly Interface) ASIC
The SARI ASIC is the interface that controls the data ßow between the TDM Bus
and the i960 Host Processor. The SARI ASIC has a 768-cell queue and provides the
trafÞc management features of the 9A686-04.
and the i960 Host Processor. The SARI ASIC has a 768-cell queue and provides the
trafÞc management features of the 9A686-04.
CTM (Cell Transfer Matrix) ASICs
The 9A686-04 has four CTM ASICs that provide four interfaces each between the
TDM Bus and the CTM Backplane located in the SmartSwitch 9500 chassis. Each
interface is a full-duplex connection with a raw throughput capacity of 2 Gbps. In
addition, the CTM ASICs perform all trafÞc management between the 9A686-04
and the CTM backplane.
TDM Bus and the CTM Backplane located in the SmartSwitch 9500 chassis. Each
interface is a full-duplex connection with a raw throughput capacity of 2 Gbps. In
addition, the CTM ASICs perform all trafÞc management between the 9A686-04
and the CTM backplane.
Utopia (Universal Test and Operation Physical Interface) ASICs
The 9A686-04 has four Utopia ASICs whose role is to process ATM cells from the
ANIMs to the TDM Bus, and vice versa. In addition, the Utopia ASICs are
responsible for performing path lookups and outbound header translation.
ANIMs to the TDM Bus, and vice versa. In addition, the Utopia ASICs are
responsible for performing path lookups and outbound header translation.
i960HD Processor
The i960HD processor, working with the Þve types of ASICs deÞned earlier, is
responsible for distributed management functions, signalling, SNMP
management and serving as the in-band management LAN Emulation Client
(LEC) for the module. The i960 also supports out-of-band management interfaces.
responsible for distributed management functions, signalling, SNMP
management and serving as the in-band management LAN Emulation Client
(LEC) for the module. The i960 also supports out-of-band management interfaces.