Zhone 7995 Betriebsanweisung
A. Configuration Options
7990-A2-GB20-20
September 2004
A-9
Payload Rate
Possible Settings: 64 – 2304 kbps in 64k increments
Default Setting: 192 kbps
Default Setting: 192 kbps
Specifies the payload rate of the port. This field is read-only unless the DSL Line Rate is
200 kbps (see
200 kbps (see
Table A-1, DSL Interface Options
), with 64, 128, and 192 kbps being the
only selections available.
) and the device is in Fixed Rate mode. The STU-C configures the
payload rate for the STU-R when in Fixed Rate mode. If the unit is in Adaptive Rate
mode (Max DSL Rate = Min DSL Rate, see
mode (Max DSL Rate = Min DSL Rate, see
Table A-1, DSL Interface Options
), the
Payload Rate will default to the highest rate that is closest to the DSL adaptive rate
achieved.
achieved.
64 – 2304 – Sets the payload rate in kbps when Fixed Rate mode is enabled.
Transmit Clock Source
Possible Settings: Internal, External
Default Setting: Internal
Default Setting: Internal
Specifies whether the transmitted data for the synchronous data port is clocked using an
internal clock provided by the STU-C or an external clock provided by the DTE connected
to the synchronous data port.
internal clock provided by the STU-C or an external clock provided by the DTE connected
to the synchronous data port.
Transmit Clock Source appears only when DSL Mode is set to STU-C (see
) and the device is in Fixed Rate mode.
Internal – Indicates the clock is provided internally by the unit on the TXC interchange
circuit DB (CCITT 114).
circuit DB (CCITT 114).
External – Indicates the clock is provided externally by the DTE on the XTXC interchange
circuit DA (CCITT 113). Use this selection if the clock source is set to the data port.
circuit DA (CCITT 113). Use this selection if the clock source is set to the data port.
Invert Transmit Clock
Possible Settings: Disable, Enable
Default Setting: Disable
Default Setting: Disable
Specifies whether the clock supplied by the the unit on the TXC interchange circuit DB
(ITU-T 114) is phase inverted with respect to the Transmitted Data interchange circuit BA
(ITU-T 103). This configuration option is useful when an excessive cable length between
the unit and the DTE causes errors.
(ITU-T 114) is phase inverted with respect to the Transmitted Data interchange circuit BA
(ITU-T 103). This configuration option is useful when an excessive cable length between
the unit and the DTE causes errors.
) and Transmit Clock Source is set to External.
Disable – Indicates TXC supplied by the unit on this port is not phase inverted.
Enable – Indicates TXC supplied by the unit on this port is phase inverted.
Table A-4.
Synchronous Data Port Options – Model 7995 (2 of 4)