Fujitsu Intel Xeon E7540 S26361-F4007-L540 Datenbogen

25

I

CC_TDC

I

CC

 for Dual-Core Intel Xeon processor 

7000 series Thermal Design Current
2.8 - FMB GHz

130

A

 

20,

NOTES:
1.  Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on silicon 

characterization, however they may be updated as further data becomes available.

2.  Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have 

different VID settings.

3.  These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. 

 for more information. 

4.  The voltage specification requirements are measured across vias on the platform for the VCCSENSE and VSSSENSE pins close 

to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M

Ω minimum impedance. The 

maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled 
in the scope probe. 

5. Refer to 

 and corresponding 

. The processor should not be subjected to any static V

CC

 level that exceeds the 

V

CC_MAX

 associated with any particular current. Failure to adhere to this specification can shorten processor lifetime.

6. Minimum V

CC

 and maximum I

CC

 are specified at the maximum processor case temperature (T

CASE

) shown in 

. I

CC_MAX

 

is specified at the relative V

CC_MAX

 point on the V

CC

 load line. The processor is capable of drawing I

CC_MAX

 for up to 10 ms. 

Refer to 

 for further details on the average processor current draw over various time durations.

7.  FMB is the flexible motherboard guideline. These guidelines are for estimation purposes only. See 

 for further details 

on FMB guidelines.

8.  This specification represents the V

CC

 reduction due to each VID transition. See 

. AC timing requirements will be 

included in future revisions of this document.

9.  This specification refers to the potential total reduction of the load line due to VID transitions below the specified VID.
10. V

TT

 must be provided via a separate voltage source and must not be connected to V

CC

. This specification is measured at the pin.

11. Baseboard bandwidth is limited to 20 MHz.
12. This specification refers to a single processor with R

TT

 disabled. Please note the end agent and middle agent may not require 

I

TT

(max) simultaneously. Details will be provided in future revisions of this document.

13. This specification refers to platforms implementing a power delivery system that complies with VR 10.2 guidelines. Please see 

the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.2 Design Guidelines for further details.

14. This specification refers to a single processor with R

TT

 enabled. Please note the end agent and middle agent may not require 

I

TT

(max) simultaneously. This parameter is based on design characterization and not tested.

15. These specifications apply to the PLL power pins VCCA, VCCIOPLL, and VSSA. See 

 for details. These 

parameters are based on design characterization and are not tested.

16. This specification represents a total current for all GTLREF pins.
17. The current specified is also for HALT State.
18. This specification applies to both the HALT and Enhanced HALT States.
19. The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the 

assertion of the PROCHOT# signal is the maximum I

CC

 for the processor.

20. I

CC_TDC

 (Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely 

and should be used for the voltage regulator temperature assessment. The voltage regulator is responsible for monitoring its 
temperature and asserting the necessary signal to inform the processor of a thermal excursion. Please see the applicable design 
guidelines for further details. The processor is capable of drawing I

CC_TDC

 indefinitely. Refer to 

 for further details on 

the average processor current draw over various time durations. This parameter is based on design characterization and is not 
tested.