Intel Xeon L3406 CM80616005010AA Benutzerhandbuch

108

Datasheet, Volume 2

1

 

RO

0

Non Fatal Error Reporting Enable
This bit applies only to the PCI Express/DMI ports. The bit controls the 

reporting of non-fatal errors that IIO detects on the PCI Express/DMI 

interface or any non-fatal errors that PerfMon detect.
0 = Reporting of Non Fatal error detected by device is disabled.

1 = Reporting of Non Fatal error detected by device is enabled.
Refer to the latest PCI Express Base Specification for complete details of how 

this bit is used in conjunction with other bits to report errors.
For the PCI Express/DMI ports, this bit is not used to control the reporting of 

other internal component uncorrectable non-fatal errors (at the port unit) in 

any way.

0

RO

0

Correctable Error Reporting Enable
This bit applies only to the PCI Express/DMI ports. The bit controls the 

reporting of correctable errors that IIO detects on the PCI Express/DMI 

interface
0 = Reporting of link Correctable error detected by the port is disabled.

1 = Reporting of link Correctable error detected by port is enabled.
Refer to the latest PCI Express Base Specification for complete details of how 

this bit is used in conjunction with other bits to report errors.
For the PCI Express/DMI ports, this bit is not used to control the reporting of 

other internal component correctable errors (at the port unit) in any way.