Intel Xeon L3406 CM80616005010AA Benutzerhandbuch
Produktcode
CM80616005010AA
Processor Uncore Configuration Registers
242
Datasheet, Volume 2
4.10.5
MC_CHANNEL_0_DDR3CMD
MC_CHANNEL_1_DDR3CMD
DDR3 Configuration Command. This register is used to issue commands to the DIMMs
such as MRS commands. The register is used by setting one of the *_VALID bits along
with the appropriate address and destination RANK. The command is then issued
directly to the DIMM. Care must be taken in using this register as there is no
enforcement of timing parameters related to the action taken by a DDR3CMD write.This
register has no effect after MC_CONROL>INIT_DONE is set.
such as MRS commands. The register is used by setting one of the *_VALID bits along
with the appropriate address and destination RANK. The command is then issued
directly to the DIMM. Care must be taken in using this register as there is no
enforcement of timing parameters related to the action taken by a DDR3CMD write.This
register has no effect after MC_CONROL>INIT_DONE is set.
Device:
4, 5
Function:
0
Offset:
60h
Access as a DWord
Bit
Attr
Default
Description
31:29
RO
0
Reserved
28
RW
0
PRECHARGE_VALID
Indicates current command is for a precharge command.
Indicates current command is for a precharge command.
27
RW
0
ACTIVATE_VALID
Indicates current command is for an activate command.
Indicates current command is for an activate command.
26
RW
0
REG_VALID
Indicates current command is for a registered DIMM configuration write Bit
Indicates current command is for a registered DIMM configuration write Bit
is cleared by hardware on issuance. This bit applies only to processors
supporting registered DIMMs.
25
RW
0
WR_VALID
Indicates current command is for a write CAS. Bit is cleared by hardware
Indicates current command is for a write CAS. Bit is cleared by hardware
on issuance.
24
RW
0
RD_VALID
Indicates current command is for a read CAS. Bit is cleared by hardware
Indicates current command is for a read CAS. Bit is cleared by hardware
on issuance.
23
RW
0
MRS_VALID
Indicates current command is an MRS command. Bit is cleared by
Indicates current command is an MRS command. Bit is cleared by
hardware on issuance.
22:20
RW
0
RANK
Destination rank for command.
Destination rank for command.
19:16
RW
0
MRS_BA
Bank address portion of the MRS command. The MRS_BA field corresponds
Bank address portion of the MRS command. The MRS_BA field corresponds
to BA[3:0].
15:0
RW
0
MRS_ADDR
Address used by the MRS command.
Address used by the MRS command.