Intel Xeon L3406 CM80616005010AA Benutzerhandbuch
Produktcode
CM80616005010AA
Datasheet, Volume 2
99
Processor Integrated I/O (IIO) Configuration Registers
8
RO
0
SERR Enable
For PCI Express/DMI ports, this field enables notifying the internal core
For PCI Express/DMI ports, this field enables notifying the internal core
error logic of occurrence of an uncorrectable error (fatal or non-fatal) at
the port. The internal core error logic of Integrated I/O then decides if/how
to escalate the error further (pins/message and so forth). This bit also
controls the propagation of PCI Express ERR_FATAL and ERR_NONFATAL
messages received from the port to the internal Integrated I/O core error
logic.
0 = Fatal and Non-fatal error generation and Fatal and Non-fatal error
0 = Fatal and Non-fatal error generation and Fatal and Non-fatal error
message forwarding is disabled.
1 = Fatal and Non-fatal error generation and Fatal and Non-fatal error
message forwarding is enabled.
Refer to the latest PCI Express Base Specification for details of how this bit
is used in conjunction with other control bits in the Root Control register for
forwarding errors detected on the PCI Express interface to the system core
error logic.
7
RO
0
IDSEL Stepping/Wait Cycle Control
Not applicable to internal Integrated I/O devices. Hardwired to 0.
Not applicable to internal Integrated I/O devices. Hardwired to 0.
6
RO
0
Parity Error Response
For PCI Express/DMI ports, Integrated I/O ignores this bit and always does
For PCI Express/DMI ports, Integrated I/O ignores this bit and always does
ECC/parity checking and signaling for data/address of transactions both to
and from Integrated I/O.
5
RO
0
VGA Palette Snoop Enable
Not applicable to internal Integrated I/O devices. Hardwired to 0.
Not applicable to internal Integrated I/O devices. Hardwired to 0.
4
RO
0
Memory Write and Invalidate Enable
Not applicable to internal Integrated I/O devices. Hardwired to 0.
Not applicable to internal Integrated I/O devices. Hardwired to 0.
3
RO
0
Special Cycle Enable
Not applicable to PCI Express. Hardwired to 0.
Not applicable to PCI Express. Hardwired to 0.
2
RO
0
Bus Master Enable
Controls the ability of the PCI Express port in generating/forwarding
Controls the ability of the PCI Express port in generating/forwarding
memory (including MSI writes) or I/O transactions (and not messages) or
configuration transactions from the secondary side to the primary side.
0 = The Bus Master is disabled. When this bit is 0, Integrated I/O root
0 = The Bus Master is disabled. When this bit is 0, Integrated I/O root
ports will treat upstream PCI Express memory writes/reads, IO
writes/reads, and configuration reads and writes as unsupported
requests (and follow the rules for handling unsupported requests).
This behavior is also true towards transactions that are already
pending in the Integrated I/O root port’s internal queues when the
BME bit is turned off.
1 = Enables the PCI Express ports to generate/forward memory,
configuration, or I/O read/write requests.
1
RO
0
Memory Space Enable
0 = Disables a PCI Express port’s memory range registers to be decoded
0 = Disables a PCI Express port’s memory range registers to be decoded
as valid target addresses for transactions from primary side.
1 = Enables a PCI Express port’s memory range registers to be decoded as
valid target addresses for transactions from primary side.
Note that if a PCI Express port’s MSE bit is clear, that port can still be target
of any memory transaction if subtractive decoding is enabled on that port.
(Sheet 2 of 3)
Register: PCICMD
Device:
8
Function:
0-3
Offset:
04h
Bit
Attr
Default
Description