Intel E6600 AT80571PH0832ML Datenbogen
Produktcode
AT80571PH0832ML
Electrical Specifications
22
Datasheet
2.7.1
FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers, which use GTLREF[1:0] as a reference level. In
this document, the term “GTL+ Input” refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output
group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent on the rising edge of BCLK0 (ADS#, HIT#, HITM#, and so forth) and the
second set is for the source synchronous signals that are relative to their respective
strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous
signals are still present (A20M#, IGNNE#, and so forth) and can become active at any
time during the clock cycle.
synchronous, and asynchronous.
NOTES:
1.
1.
for signal descriptions.
2.
In processor systems where no debug port is implemented on the system board, these
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
3.
The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See
processor configuration options. See
for details.
4.
PROCHOT# signal type is open drain output and CMOS input.
Table 7.
FSB Signal Groups
Signal Group
Type
Signals
1
GTL+ Common
Clock Input
Clock Input
Synchronous to
BCLK[1:0]
BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
GTL+ Common
Clock I/O
Clock I/O
Synchronous to
BCLK[1:0]
BCLK[1:0]
ADS#, BNR#, BPM[5:0]#, BR0#
3
, DBSY#, DRDY#, HIT#,
HITM#, LOCK#
GTL+ Source
Synchronous I/O
Synchronous I/O
Synchronous to
assoc. strobe
assoc. strobe
GTL+ Strobes
Synchronous to
BCLK[1:0]
BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
CMOS
A20M#, DPRSTP#. DPSLP#, IGNNE#, INIT#, LINT0/INTR,
LINT1/NMI, SMI#
LINT1/NMI, SMI#
3
, STPCLK#, PWRGOOD, SLP#, TCK, TDI,
TMS, TRST#, BSEL[2:0], VID[7:0], PSI#
Open Drain Output
FERR#/PBE#, IERR#, THERMTRIP#, TDO
Open Drain Input/
Output
Output
PROCHOT#
4
FSB Clock
Clock
BCLK[1:0], ITP_CLK[1:0]
2
Power/Other
VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,
GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[12,10:0],
VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR#
GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[12,10:0],
VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR#
2
, VTT_OUT_LEFT,
VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
3
ADSTB0#
A[35:17]#
3
ADSTB1#
D[15:0]#, DBI0#
DSTBP0#, DSTBN0#
D[31:16]#, DBI1#
DSTBP1#, DSTBN1#
D[47:32]#, DBI2#
DSTBP2#, DSTBN2#
D[63:48]#, DBI3#
DSTBP3#, DSTBN3#