Nokia 9210i Servicehandbuch
PAMS
Technical Documentation
RAE-5
3. RF+System Module KL8
Page 3 – 60
Issue 1 04/02
Timings
Transmit power Timing
Figure 14.
Transmitter control timing diagram for all kind of TX bursts
Pout
TXC
TXP
542.8 us
Modulator power
Control
writings
writings
min 340us
or two bursts
one burst
1
3
4
5
7
unknown
Synthesizer clocking
Synthesizers are controlled via serial control bus, which consists of SDATA,
SCLK and SENA1 signals. These lines form a synchronous data transfer line.
SDATA is for the data bits, SCLK is 3.25 MHz clock and SENA1 is latch enable,
which stores the data into counters or registers. The signal SENA1 is latch en-
able also for HAGAR control register, which is used for programming some in-
ternal functions in HAGAR, e.g. in band changing. In this case SCLK and SDA-
TA are used the same way as in PLL programming.
SCLK and SENA1 signals. These lines form a synchronous data transfer line.
SDATA is for the data bits, SCLK is 3.25 MHz clock and SENA1 is latch enable,
which stores the data into counters or registers. The signal SENA1 is latch en-
able also for HAGAR control register, which is used for programming some in-
ternal functions in HAGAR, e.g. in band changing. In this case SCLK and SDA-
TA are used the same way as in PLL programming.
Table 45. Internal antenna connector
Parameter
Min.
Min.
Typ.
Max.
Unit/Notes
Operating frequency range
880
880
1880
MHz
Insertion loss in GSM band
0.2
dB
Insertion loss in DCS band
0.4
dB
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