FIC mb02 Servicehandbuch
FIC CONFIDENTIAL AND PROPRIETARY
MB02 Functional Specifications Rev. 0.3 Page 65
MB02 Functional Specifications Rev. 0.3 Page 65
FIC H/W
FIC CONFIDENTIAL AND PROPRIETARY 11-November-2002_
6
0
Reserved. Set = 0.
5
0
Reserved. Set = 0.
4
0
Reserved. Set = 0.
3
0
Reserved. Set = 0.
2
0
Reserved. Set = 0.
1
0
Reserved. Set = 0.
0
0
Reserved. Set = 0.
Bytes 8: Dial-a-Frequency Control Register N
Bits
Name
@Pup
Description
7
0
Reserved. Set = 0.
6
N6, MSB
0
5
N5
0
4
N4
0
3
N3
0
2
N2
0
1
N1
0
0
N0, LSB
0
These bits are for programming the PLL’s internal N
register. This access allows the user to
modify the CPU frequency at very high resolution
(accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such
as PCI) remain at their existing ratios
relative to the CPU clock.
Bytes 9: Dial-a-Frequency Control Register R
Bits
Name
@Pup
Description
7
0
Reserved. Set = 0.
6
R5, MSB
0
5
R4
0
4
R3
0
3
R2
0
2
R1
0
1
R0, LSB
0
MSB These bits are for programming the PLL’s
internal R register. This access allows the user to
modify the CPU frequency at very high resolution
(accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such
as PCI) remain at their existing ratios
relative to the CPU clock.
0
DAF_ENB
0
R and N register mux selection. 0 = R and N values
come from the ROM. 1 = data is loaded
from DAF (SMBus) registers.
8 SYSTEM MANAGEMENT
8.1 GPIO Set register list
8.1.1
Intel ICH4-M GPIO Configuration
Please refer to ICH4-M Datasheet for detail.
8.1.2
PMU08 GPIO Configuration
Please refer to <MB02> power management subsystem for section8. (EC<PMU08> Event/GPIO Register)
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