FIC a440 Servicehandbuch

 

Troubleshooting and Repair 

 

6-8 

FIC A440 Series Service Manual 

4-2-1 

34h 

Timer-tick interrupt test in 
progress or failure. 

All interrupts expect the timer-tick 
interrupt are masked off at the interrupt 
controllers. If a timer-tick interrupt does 
not occur during a specific time period, 
an error message is displayed on the 
screen. The system does not halt. 

4-2-2 

35h 

Shutdown test in progress or 
failure. 

A return address is stored in 40:67h and 
the processor is reset via the keyboard 
controller. If a timer tick occurs during 
this time period, an error message is 
displayed on the screen. Other failures 
are hard to detect. If possible, the BIOS 
will continue with POST, skipping the 
memory tests. 

4-2-3 

36h 

Gate A20 failure. 

To test extended memory, the processor 
must be placed in protected mode and 
the A20 line must be enabled. For the 
memory tests, the BIOS generally uses 
the keyboard controller to enable A20. If 
the A20 line is not properly set during the 
memory test, an error message is 
displayed on the screen and the memory 
test are suspended. The system does 
not halt. 

4-2-4 

37h 

Unexpected interrupt in 
protected mode. 

During the memory tests, the processor 
is placed in protected mode. All 
interrupts in the interrupt descriptor table 
are initialized to point to special handler 
that displays a message on the screen. 
All hardware interrupt are disabled. The 
system does not halt when an 
unexpected interrupt occurs. 

4-3-1 

38h 

RAM test of memory above 
64K in progress or failure. 

The memory above the first 64K is tested 
with a rolling ones test and a pattern test. 
All success and failure messages are 
displayed on the screen and POST will 
continue. 

4-3-2 

3Ah 

Programmable interval timer 
channel 2 test in progress or 
failure. 

Over a period of time, the current count 
values in timer 2 are read and 
accumulated by ORing them into the 
values read so far. It is expected that 
during the time period, all bits will be set. 
If an error is detected, an error message 
will be displayed on the screen and 
POST will continue. 

4-3-4 

3Bh 

Real-time clock test in 
progress or failure. 

Over a period of time, the Update-In-
Progress bit of  Status Register A of the 
real-time clock is read and tested. The bit 
should toggle from 0 to 1 within the time 
period.