MiTAC w130 Servicehandbuch
10
Support I2C Index read/write and block read/write operations.
Use external 14.318MHz crystal.
1.3.3 Intel 855-GM GMCH IGUI 3D Graphic DDR/SDR Chipset
Intel 855-GM GMCH IGUI Host Memory Controller integrates a high
performance host interface for Intel Banias processor, a high performance
2D/3D Graphic Engine, a high performance memory controller, an AGP
4X interface, and Intel®’ I/O Hub architecture INTEL 82801DBM ICH4-M.
2D/3D Graphic Engine, a high performance memory controller, an AGP
4X interface, and Intel®’ I/O Hub architecture INTEL 82801DBM ICH4-M.
Intel 855-GM GMCH Host Interface features the AGTL & AGTL+
compliant bus driver technology with integrated on-die termination to
support Intel Pentium-M processors. 855-GM GMCH provides a 12-deep
In-Order-Queue to support maximum outstanding transactions up to 12. It
integrated a high performance 2D/3D Graphic Engine, Video Accelerator
and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for
the Intel Pentium-M series based PC systems. It also integrates a high
performance 2.1GB/s DDR266 Memory controller to sustain the
bandwidth demand from the integrated GUI or external AGP master, host
processor, as well as the multi I/O masters. In addition to integrated GUI,
855-GM GMCH also can support external AGP slot with AGP 1X/2X/4X
capability and Fast Write Transactions. A high bandwidth and mature
Intel®’ I/O Hub architecture is incorporated to connect 855-GM GMCH
and INTEL 82801DBM ICH4-Mtogether. Intel®’ I/O Hub architecture is
developed into three layers, the Multi-threaded I/O Link Layer delivering
1.2GB bandwidth to connect embedded DMA Master devices and external
PCI masters to interface to Multi-threaded I/O Link layer, the
Multi-threaded I/O Link Encoder/Decoder in INTEL 82801DBM ICH4-M to
transfer data w/ 533 MB/s bandwidth from/to Multi-threaded I/O Link layer
to/from 855-GM GMCH, and the Multi-threaded I/O Link Encoder/Decoder
in 855-GM GMCH to transfer data w/ 533 MB/s from/to Multi-threaded I/O
Link layer to/from INTEL 82801DBM ICH4-M.
support Intel Pentium-M processors. 855-GM GMCH provides a 12-deep
In-Order-Queue to support maximum outstanding transactions up to 12. It
integrated a high performance 2D/3D Graphic Engine, Video Accelerator
and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for
the Intel Pentium-M series based PC systems. It also integrates a high
performance 2.1GB/s DDR266 Memory controller to sustain the
bandwidth demand from the integrated GUI or external AGP master, host
processor, as well as the multi I/O masters. In addition to integrated GUI,
855-GM GMCH also can support external AGP slot with AGP 1X/2X/4X
capability and Fast Write Transactions. A high bandwidth and mature
Intel®’ I/O Hub architecture is incorporated to connect 855-GM GMCH
and INTEL 82801DBM ICH4-Mtogether. Intel®’ I/O Hub architecture is
developed into three layers, the Multi-threaded I/O Link Layer delivering
1.2GB bandwidth to connect embedded DMA Master devices and external
PCI masters to interface to Multi-threaded I/O Link layer, the
Multi-threaded I/O Link Encoder/Decoder in INTEL 82801DBM ICH4-M to
transfer data w/ 533 MB/s bandwidth from/to Multi-threaded I/O Link layer
to/from 855-GM GMCH, and the Multi-threaded I/O Link Encoder/Decoder
in 855-GM GMCH to transfer data w/ 533 MB/s from/to Multi-threaded I/O
Link layer to/from INTEL 82801DBM ICH4-M.
An Unified Memory Controller supporting DDR266 DRAM is incorporated,
delivering a high performance data transfer to/from memory subsystem
from/to the Host processor, the integrated graphic engine or external AGP
master, or the I/O bus masters. The memory controller also supports the
Suspend to RAM function by retaining the CKE# pins asserted in ACPI S3
state in which only AUX source deliver power. The 855-GM GMCH adopts
the Shared Memory Architecture, eliminating the need and thus the costs
from/to the Host processor, the integrated graphic engine or external AGP
master, or the I/O bus masters. The memory controller also supports the
Suspend to RAM function by retaining the CKE# pins asserted in ACPI S3
state in which only AUX source deliver power. The 855-GM GMCH adopts
the Shared Memory Architecture, eliminating the need and thus the costs