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iSPAN 4532 PMC ATM over OC-3c/STM-1 Communications Controller
4532 Architecture
The iSPAN 4532 PMC ATM Over OC3/STM-1 Communications
Controller is a member of the Interphase line of MPC8260A-based
controllers for carrier-class telecommunications environments.
The software selectable interface for SONET OC-3c or SDH STM-1
makes the 4532 a universal interface module and enables maximum
fl exibility to support multiple international standard variants with
just one board.
The 64-bit, 66 MHz 60x data bus connects the core RISC CPU to
the 64-bit wide SDRAM memory and the local side of the Tundra
PowerSpan PCI bridge. I/O transfers across the bridge to the PCI
bus are executed at 32-bits, 33 MHz or 66 MHz. Also connected to
the 60x data bus is an 16-bit 8 MB downloadable Flash memory (4
MB of 8-bit Flash on original 4532 models) that can be used to store
boot code and operational fi rmware.
The MPC8260A CPM co-processor interfaces to the SONET/
SDH ATM framer via a master UTOPIA bus interface, which in
turn connects to the optical transceiver that connects to the
transmission line. The MPC8260A CPM performs all ATM layer
functions, including ATM layer, and up to the Common Part
Convergence Sublayer (CPCS) AAL functionality. The CPM has
separate and unimpeded access to a second block of 8 MB of
SDRAM memory, which can be used for storing virtual connection
lookup tables and traffi c descriptors.
A second slave-mode UTOPIA interface from the 8260A CPM
coprocessor is available to a carrier card via the PMC P3 connector,
and can carry ATM traffi c to and from the carrier card. In this
mode, the 4532 can be used as the front-end to an ATM switch as a
peripheral I/O card. Furthermore, the 8260A core RISC CPU can be
disabled, in which case the 4532 utilizes the CPM co-processor and
the ATM framer only to act as the physical I/O interconnect to an
ATM link.
Controller is a member of the Interphase line of MPC8260A-based
controllers for carrier-class telecommunications environments.
The software selectable interface for SONET OC-3c or SDH STM-1
makes the 4532 a universal interface module and enables maximum
fl exibility to support multiple international standard variants with
just one board.
The 64-bit, 66 MHz 60x data bus connects the core RISC CPU to
the 64-bit wide SDRAM memory and the local side of the Tundra
PowerSpan PCI bridge. I/O transfers across the bridge to the PCI
bus are executed at 32-bits, 33 MHz or 66 MHz. Also connected to
the 60x data bus is an 16-bit 8 MB downloadable Flash memory (4
MB of 8-bit Flash on original 4532 models) that can be used to store
boot code and operational fi rmware.
The MPC8260A CPM co-processor interfaces to the SONET/
SDH ATM framer via a master UTOPIA bus interface, which in
turn connects to the optical transceiver that connects to the
transmission line. The MPC8260A CPM performs all ATM layer
functions, including ATM layer, and up to the Common Part
Convergence Sublayer (CPCS) AAL functionality. The CPM has
separate and unimpeded access to a second block of 8 MB of
SDRAM memory, which can be used for storing virtual connection
lookup tables and traffi c descriptors.
A second slave-mode UTOPIA interface from the 8260A CPM
coprocessor is available to a carrier card via the PMC P3 connector,
and can carry ATM traffi c to and from the carrier card. In this
mode, the 4532 can be used as the front-end to an ATM switch as a
peripheral I/O card. Furthermore, the 8260A core RISC CPU can be
disabled, in which case the 4532 utilizes the CPM co-processor and
the ATM framer only to act as the physical I/O interconnect to an
ATM link.
Processor/Memory
• PowerQUICC II (MPC8260A) 64-bit RISC processor allows full
support of various communications protocols, reducing host CPU
processing
• Dual bus architecture: 64-bit 60x bus and 32-bit local
CPM bus
• 300 MHz core, 200 MHz CPM, 570 MIPs CPU
• 128 MB 64-bit SDRAM memory
• 8 MB downloadable 16-bit Flash memory
• Dual bus architecture: 64-bit 60x bus and 32-bit local
CPM bus
• 300 MHz core, 200 MHz CPM, 570 MIPs CPU
• 128 MB 64-bit SDRAM memory
• 8 MB downloadable 16-bit Flash memory
• 8 MB 32-bit Connection Memory
Interfaces
• One front access or rear access software selectable OC-3/STM-1
interface (rear access via PCI Interface Module (PIM))
• Long-range single-mode, intermediate-range single-mode and
short-range multi-mode fi ber interfaces available:
• Long-range single-mode fi ber: Up to 24.85 miles/40 km
• Intermediate-range single-mode fi ber: Up to 12.4 miles/20 km
• Short-range multimode fi ber: Up to 1.24 miles/2 km
• ATM over WAN SONET framer supports direct connection to long
• Intermediate-range single-mode fi ber: Up to 12.4 miles/20 km
• Short-range multimode fi ber: Up to 1.24 miles/2 km
• ATM over WAN SONET framer supports direct connection to long
haul optical network
• Support for SONET and SDH overhead channels, including
facility Data Link channels, alarms and indications, error and
performance monitoring; connects directly to SONET/SDH
facilities
performance monitoring; connects directly to SONET/SDH
facilities
• One Fast Ethernet interface on the front panel for remote boot or
LAN capability with 10/100 Base-T transceiver
• One front access RS-232 TTY port provided on a 2.5 mm stereo
jack
• Optional JTAG debug port
Optional Rear Access via PCI Interface Module (PIM)
• Standard PCI Interface Module (PIM) design
• Single OC-3/STM-1 interface supporting long range single-mode,
• Single OC-3/STM-1 interface supporting long range single-mode,
intermediate range single-mode, and short-range multimode fi ber
interfaces available (see above)
interfaces available (see above)
• Designed for use with any VITA 36-199x PIM-compatible Rear
Transition Module (RTM)
PCI Interface
• 32-bit, 33 MHz or 66 MHz PCI interface on P1 & P2 connectors
• PCI 2.2 master/target bus interface with I
• PCI 2.2 master/target bus interface with I
2
O messaging unit and
four linked list DMA
• 32-bit DMA exchanges for high-transfer performance
Telecom Clock Management
• The line interface can be confi gured in LT (clock slave) or NT
(clock master) mode.
• Three line synchronization sources:
• Free running internal clock
• Recovered clock (loop back timing)
• Network reference (via P3)
• The recovered line clock is available to the carrier board via the
• Free running internal clock
• Recovered clock (loop back timing)
• Network reference (via P3)
• The recovered line clock is available to the carrier board via the
P3 connector.
4532 Hardware
Powerful Features for Next-Generation Telecom Applications
Tech Specs
Architecture
Bus Type
Bus Type
PMC (PCI 2.2 Compliant)
Bus Data Transfer
32-bit, 33/66 MHz
Open Boot Interface
IEEE 1275
Memory 128
MB
SDRAM
Mechanical
Length
Length
149 mm (5.86 in.)
Width
74 mm (2.9 in.)
Indicators
Board Operational, Link active
Operating Environment
Power Dissipation
Power Dissipation
5 V: 0.4 A, 3.3 V: 1.7 A
Temperature
0 to 55 ˚C (32 to 131 ˚F)
Storage Range
–40 to 80 ˚C (–40 to 176 ˚F)
Relative Humidity
5% to 95% non-condensing
Altitude
0 to 15,000 ft.