ZTE Corporation ZM8300G Benutzerhandbuch
ZTE ZM8300G Module Hardware User Manual
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system configurations (restricted by the SPI protocol). Figure 3-10 illustrates the system
configurations.
Figure 3-10 SPI System Configurations
Pay attention to the following points during design:
1) If the SPI bus reaches the highest frequency during running, its priority must be higher
than the priorities of other BLSP bus interfaces.
2) If one group of SPI buses is shared by multiple devices, ensure that these devices are
close to each other, with the goal of avoiding signal integrity problems caused by long bus
branches.
3) The SPI interface provided by the ZM8300G module is a 1.8 V IO interface. If the
ZM8300G module needs to work with a peripheral that uses a different level, add a level
conversion circuit. Figure 3-11 illustrates the recommended level conversion circuit. The level
conversion chip (TI: TXB0104RUTR) is recommended.
ZM8300
Level
Shift
Peripheral
Chip
VIO
VCCA
OE
VCCB
GND
VCC_3V3
S
P
I
(1
.8
v
)
A1~A4
GND
GND
B1~B4
S
P
I
(3
.3
v
)
Figure 3-11 SPI Level Conversion Circuit