Billion Electric Co. Ltd. BIL-SIM7100C Benutzerhandbuch

SIM7100C_User Manual_V1.01

41

T(sync)

PCM_SYNC cycle time

–

125

–

μs

T(synch)

PCM_SYNC high time

400

500

–

ns

T(syncl)

PCM_SYNC low time

–

124.5 –

μs

T(clk)

PCM_CLK cycle time

–

488

–

ns

T(clkh)

PCM_CLK high time

–

244

–

ns

T(clkl)

PCM_CLK low time

–

244

–

ns

T(susync)

PCM_SYNC setup time high before falling edge of
PCM_CLK

60

–

–

ns

T(hsync)

PCM_SYNC hold time after falling edge of
PCM_CLK

60

–

–

ns

T(sudin)

PCM_IN setup time before falling edge of
PCM_CLK

50

–

–

ns

T(hdin)

PCM_IN hold time after falling edge of PCM_CLK

10

–

–

ns

T(pdout)

Delay from PCM_CLK rising to PCM_OUT valid

–

–

350

ns

T(zdout)

Delay from PCM_CLK falling to PCM_OUT
HIGH-Z

–

160

–

ns

The mode of SIM7100C PCM can be configured by AT command “AT+CPCM and AT+CPCMFMT”, and
the default configuration is master mode using short sync data format with 2.048MHz PCM_CLK and 8