E F Johnson Company 2422001-1 Benutzerhandbuch
CIRCUIT DESCRIPTION
6-29
August 2000
Part No. 001-2001-200
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Flash Memory, RAM, non-volatile EEPROM.
•
I/O chip select to allow the addressing of data
latches for Input/Output.
latches for Input/Output.
•
Read/Write selection to be sent and received on the
Controller Backplane.
Controller Backplane.
•
Clock line, data line and chip select line from the
IAC to load the Receiver and Exciter synthesizers.
IAC to load the Receiver and Exciter synthesizers.
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Serial communication circuitry and processes for
the High Speed Data Bus (HSDB).
the High Speed Data Bus (HSDB).
•
Asynchronous parallel communication to the other
cards, i.e. alarm input and output circuitry.
cards, i.e. alarm input and output circuitry.
•
AC Power Failure indication from the IAC.
•
Provides an output from the IAC to the power
amplifier to control the output power.
amplifier to control the output power.
•
Exciter Logic Push-To-Talk (PTT).
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Receiver synthesizer lock, Exciter synthesizer lock,
thermal level from the power amplifier, VSWR
level from the PA, forward power level, RSSI signal
level, audio levels from the MAC, Receiver and
Exciter from the IAC.
thermal level from the power amplifier, VSWR
level from the PA, forward power level, RSSI signal
level, audio levels from the MAC, Receiver and
Exciter from the IAC.
6.9.2 MAIN CONTROLLER MICROPROCES-
SOR
U27 contains the main software and control over
the repeater (see Figure 6-12).
The main controller (U27) is a VLSI (Very Large
Scale Integration) CMOS 16-bit single chip computer
with an 8-bit external data bus. This processor has
software compatibility with the V20 (8086/8088),
faster memory access, superior interrupt processing
ability, and enhanced control of internal peripherals.
This ROMless processor has a variety of on-chip com-
ponents including 256 bytes of RAM, serial and paral-
lel inputs/outputs, comparator port lines and timers.
with an 8-bit external data bus. This processor has
software compatibility with the V20 (8086/8088),
faster memory access, superior interrupt processing
ability, and enhanced control of internal peripherals.
This ROMless processor has a variety of on-chip com-
ponents including 256 bytes of RAM, serial and paral-
lel inputs/outputs, comparator port lines and timers.
Eight banks of registers are mapped into internal
RAM below an additional 256-byte special function
register (SFR) area that is used to control on-chip
register (SFR) area that is used to control on-chip
peripherals. Internal RAM and the SFR area are
together and can be relocated anywhere in the 1M-
byte address space. This maintains compatibility with
existing system memory maps.
together and can be relocated anywhere in the 1M-
byte address space. This maintains compatibility with
existing system memory maps.
The two microprocessors and USART (U22) are
reset by integrated circuit U17. Reset occurs when
power is turned on, when the 5V supply drops below a
threshold level or the reset switch (S1) is active.
power is turned on, when the 5V supply drops below a
threshold level or the reset switch (S1) is active.
When a microprocessor is reset, several internal
registers are cleared and the program is started over
from the beginning. Low-voltage reset prevents
improper operation resulting from low-voltage
conditions.
from the beginning. Low-voltage reset prevents
improper operation resulting from low-voltage
conditions.
When power is turned on, the RESET output
U17, pin 6 is initially high and the inverted RESET
output U17, pin 5 is initially low. Once the 5V supply
stabilizes, these outputs remain in these states for
approximately 100 ms to ensure that reset occurs.
output U17, pin 5 is initially low. Once the 5V supply
stabilizes, these outputs remain in these states for
approximately 100 ms to ensure that reset occurs.
This time delay is set by capacitor C14 connected
to U17, pin 3. If the 5V supply drops below a nominal
level, the RESET outputs change states and micropro-
cessor operation is interrupted until the 5V supply
returns to normal. C3 prevents fast transients on the
5V supply from causing reset.
level, the RESET outputs change states and micropro-
cessor operation is interrupted until the 5V supply
returns to normal. C3 prevents fast transients on the
5V supply from causing reset.
Manual reset can be accomplished by pressing
push-button switch S1. When U17, pin 2 goes low,
U17 goes into the reset sequence described.
U17 goes into the reset sequence described.
6.9.3 HIGH SPEED DATA BUS MICROPROCES-
SOR (U13)
The HSDB processor (U13) on the MPC pro-
vides the interface with the HSDB. It monitors data
on this bus and also transmits data on to this bus when
necessary. Information on this bus indicates which
repeaters are in use and also which mobiles are using
the system. This information is used by the repeater to
encode data messages to the mobiles that are monitor-
ing that channel. These messages also include infor-
mation on which repeater is free and current system
priority.
on this bus and also transmits data on to this bus when
necessary. Information on this bus indicates which
repeaters are in use and also which mobiles are using
the system. This information is used by the repeater to
encode data messages to the mobiles that are monitor-
ing that channel. These messages also include infor-
mation on which repeater is free and current system
priority.