E F Johnson Company 2422001-1 Benutzerhandbuch
6-45
August 2000
Part No. 001-2001-200
MAIN PROCESSOR CARD BLOCK DIAGRAM
FIGURE 6-17
FOLDOUT
A0-A19
ADDRESS BUS (19:0)
+5V
U15
LED DRIVER
LPTT
U26
U27
MAIN MICROPROCESSOR
DS1
DISPLAY DRIVER
A
B
C
D
BALANCED Rx/Tx
U24
IRDB-
RIDB+
DE
D
R
SWITCH TxD
SWITCH RxD
U20C
U6A
U16F
PO0
PO1
PO2
PO3
PO4
PO5
DMARQ0
DMAAKO
TC0
DMARQ1
READ
WRITE
MREQ
READ
WRITE
PT2
MREQ
R/W
RxD0
TxD0
RxD1
TxD1
INT POLL
INTP0 INTP1 MSTB
UART
U22
RD
WR
RxRDY
TxE
MSTB
D0-D7
D0-D7
U16D
U16C
MODEM DCD 4
COMPUTER Tx 2
COMPUTER Rx 3
1
J1
RxD
TxD
MPC
PROGRAMMING PORT
U2
Y3
U21
2
6
10
14
12
8
4
13
9
5
1
3
7
11
76800
38400
19200
9600
4800
2400
1200
1200
CP
BAUD RATE
J3
CLOCK
TxC
RxC
U6B
U13
P3-1
P3-0
P1-3
D0-D7
T OUT
CS
RST
P1-1
P3-7
P3-6
HIGH-SPEED DATA BUS
MICROPROCESSOR
ALE
PSEN
A8-A15
P1-2
P1-0
A13
A14
A15
U3
A
B
C
Y0
Y1
Y2
ADDRESS/DATA BUS (8:15)
*
U1
CS1
A0-A7
D0-D7
A8-A12
WE
OE
U14
OE
D0-D7
A8-A13
ADDRESS BUS (7:0)
A0-A7
EEPROM
RAM
ADDRESS
SELECT
A0-A7
D0-D7
U8
CEN
LOWER
ADDRESS LATCH
U7B
U2A
U2B
U6D
U9
DOR
SO
DE
ADDRESS BUS (7:0)
A0-A7
D0-D7
MR
DIR
S1
TX FIFO
PROCESSOR TO PROCESSOR COMMUNICATION FIFOs
U20D
U6C
READY
PO6
PT1
PT0
A0-A7
DIR
MR
DOR
SO
U10
S1
DE
U2C
U7A
READ
WRITE
X2
X1
Y1
10 MHz
10 MHz
D0-D7
U17
RST1
RESET
A0-A19
RST2
RES IN
S1
RESET
U25
DQ0-DQ7
OE
WE
Vpp
CE
A0-A16
FLASH MEMORY
DATA BUS (7:0)
U20B
U20A
Y2
Y0
Y1
U4
U5
C
B
A
G2B
A13
A14
A15
O15
O14
D
C
B
A
A19
A18
A17
A16
O13
O0
O11
U28
CE
DE
WE
D0-D7
A0-A12
RAM
U18
G
A0-A14
EPROM
D0-D7
W
E
RESET
U2F
HSDB -
HSDB +
U31
U30
Y0-Y3
U32A
OE
U2F/U31B
A
B
DE
R
DE
U23
U16B
U32B
OE
Y0-Y3
RST
T OUT
READY
U30A/U31A
Q2/Q3
U11
+5V
EPROM
FLASH
Vpp