Intel 2760QM FF8062701065300 Benutzerhandbuch
Produktcode
FF8062701065300
Electrical Specifications
50
Datasheet, Volume 1
The PECI interface operates at a nominal voltage set by V
TTD
. The set of DC electrical
specifications shown in
Table 7-13
is used with devices normally operating from a V
TTD
interface supply.
7.1.4.1
Input Device Hysteresis
The PECI client and host input buffers must use a Schmitt-triggered input design for
improved noise immunity. Refer to
improved noise immunity. Refer to
Figure 7-1
and
Table 7-13
.
7.1.5
System Reference Clocks (BCLK{0/1}_DP,
BCLK{0/1}_DN)
BCLK{0/1}_DN)
The processor core, processor uncore, PCI Express*, and DDR3 memory interface
frequencies are generated from BCLK{0/1}_DP and BCLK{0/1}_DN signals. The
processor maximum core frequency and DDR memory frequency are set during
manufacturing. It is possible to override the processor core frequency setting using
software. This permits operation at lower core frequencies than the factory set
maximum core frequency.
frequencies are generated from BCLK{0/1}_DP and BCLK{0/1}_DN signals. The
processor maximum core frequency and DDR memory frequency are set during
manufacturing. It is possible to override the processor core frequency setting using
software. This permits operation at lower core frequencies than the factory set
maximum core frequency.
The processor core frequency is configured during reset by using values stored within
the device during manufacturing. The stored value sets the lowest core multiplier at
which the particular processor can operate. If higher speeds are desired, the
appropriate ratio can be configured using the IA32_PERF_CTL MSR (MSR 199h); Bits
15:0.
the device during manufacturing. The stored value sets the lowest core multiplier at
which the particular processor can operate. If higher speeds are desired, the
appropriate ratio can be configured using the IA32_PERF_CTL MSR (MSR 199h); Bits
15:0.
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with
exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP,
BCLK{0/1}_DN inputs are provided in
(PLL), which requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with
exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP,
BCLK{0/1}_DN inputs are provided in
Table 7-14
.
7.1.5.1
PLL Power Supply
An on-die PLL filter solution is implemented on the processor. Refer to
Table 7-9
and
Table 7-10
for DC specifications.
Figure 7-1.
Input Device Hysteresis
PECI High Range
-V
TTD
-Maximum V
P
-Minimum V
P
PECI Low Range
-PECI Ground
-Minimum V
N
-Maximum V
N
Minimum
Hysteresis
Hysteresis
Valid Input
Signal Range
Signal Range