Intel 1.00 GHz YK80542KC0013M Benutzerhandbuch

105

THRMALERT# is asserted when the measured temperature from the processor thermal diode 
equals or exceeds the temperature threshold data programmed in the high-temp (THIGH) or low-
temp (TLOW) registers on the sensor. This signal can be used by the platform to implement 
thermal regulation features.

The Test Mode Select (TMS) signal is an IEEE 1149.1 compliant TAP specification support signal 
used by debug tools.

The TLB Purge Not Done (TND#) signal is asserted to delay completion of a TLB Purge 
instruction, even after the TLB Purge transaction completes on the system bus.

The Target Ready (TRDY#) signal is asserted by the target to indicate that it is ready to receive a 
write or implicit writeback data transfer.

The TAP Reset (TRST#) signal is an IEEE 1149.1 compliant TAP support signal used by debug 
tools.

The Write Snoop (WSNP#) signal indicates that snooping agents will snoop the memory write 
transaction

 list attributes of the Itanium 2 processor output, input, and I/O 

signals.

CPUPRES#

Low

—

Platform

DBSY_C1#

Low

BCLKp

Data 

DBSY_C2#

Low

BCLKp

Data

DRDY_C1#

Low

BCLKp

Data

DRDY_C2#

Low

BCLKp

Data

FERR#

Low

Asynchronous

PC Compatibility, 

IERR Mode