Intel 1.00 GHz YK80542KC0013M Benutzerhandbuch

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sampling BREQn# asserted by another symmetric agent, the symmetric owner deasserts BREQn# 
as soon as possible to release the bus. A symmetric owner stops issuing new requests that are not 
part of an existing locked operation on observing BPRI# asserted.

A symmetric agent can deassert BREQn# before it becomes a symmetric owner. A symmetric 
agent can reassert BREQn# after keeping it deasserted for one clock.

CCL# is the Cache Cleanse signal. It is driven on the second clock of the Request Phase on the 
EXF[2]#/Ab[5]# pin. CCL# is asserted for Memory Write transaction to indicate that a modified 
line in a processor may be written to memory without being invalidated in its caches.

CPUPRES# can be used to detect the presence of a Itanium 2 processor in a socket. A ground 
indicates that a Itanium 2 processor is installed, while an open indicates that a Itanium 2 processor 
is not installed.

The Data (D[127:0]#) signals provide a 128-bit data path between various system bus agents. 
Partial transfers require one data transfer clock with valid data on the byte(s) indicated by asserted 
byte enables BE[7:0]# and A[3]#. Data signals that are not valid for a particular transfer must still 
have correct ECC (if data bus error checking is enabled). The data driver asserts DRDY# to 
indicate a valid data transfer.

The Data/Code (D/C#) signal is used to indicate data (1) or code (0) on REQa[1]#, only during 
Memory Read transactions.

The Data Bus Busy (DBSY#) signal is asserted by the agent that is responsible for driving data on 
the system bus to indicate that the data bus is in use. The data bus is released after DBSY# is 
deasserted.

DBSY# is replicated three times to enable partitioning of the data paths in the system agents. This 
copy of the Data Bus Busy signal (DBSY#) is an input as well as an output.

DBSY# is a copy of the Data Bus Busy signal. This copy of the Data Bus Busy signal 
(DBSY_C1#) is an output only.