Intel III Xeon 700 MHz 80526KY7002M Benutzerhandbuch
Produktcode
80526KY7002M
APPENDIX
92
The BR[3:1]# (Bus Request) pins drive the BREQ[3:0]# signals on the system. The BR[3:0]# pins are interconnected in a
rotating manner to other processors’ BR[3:0]# pins. Table 55 gives the rotating interconnect between the processor and
bus signals for 4-way processor-based systems.
rotating manner to other processors’ BR[3:0]# pins. Table 55 gives the rotating interconnect between the processor and
bus signals for 4-way processor-based systems.
Table 55. BR[3:0]# Signals Rotating Interconnect, 4-Way
system
Bus Signal
Agent 0 Pins
Agent 1 Pins
Agent 2 Pins
Agent 3 Pins
BREQ0#
BR0# BR3# BR2# BR1#
BREQ1#
BR1# BR0# BR3# BR2#
BREQ2#
BR2# BR1# BR0# BR3#
BREQ3#
BR3# BR2# BR1# BR0#
Table 56 gives the interconnect between the processor and bus signals for a 2-way processor-based system.
Table 56. BR[3:0]# Signals Rotating Interconnect, 2-Way
system
Bus Signal
Agent 0 Pins
Agent 1 Pins
BREQ0# BR0# BR3#
BREQ1# BR1# BR0#
BREQ2# N/C
N/C
BREQ3# N/C
N/C
During power-up configuration, the central agent must assert its BR0# signal. All symmetric agents sample their BR[3:0]#
pins on active-to-inactive transition of RESET#. The pin on which the agent samples an active level determines its agent
ID. All agents then configure their BREQ[3:0]# signals to match the appropriate bus signal protocol, as shown in Table 57.
Table 57. Agent ID Configuration
BR0# BR1# BR2# BR3#
Agent
ID
L H H H 0
H H H L 1
H H L H 2
H L H H 3
10.1.15 CORE_AN_SENSE (O)
This signal is tied to the Vcc seen at the processor core and represents the output of the OCVR. This signal provides the
ability to monitor the stability of the OCVR in high reliability applications. The voltage seen at this pin is the actual
operating voltage of the core with integrated L2 Cache minus IR drops due to trace routing in the Cartridge.
ability to monitor the stability of the OCVR in high reliability applications. The voltage seen at this pin is the actual
operating voltage of the core with integrated L2 Cache minus IR drops due to trace routing in the Cartridge.
10.1.16 D[63:00]# (I/O)
The D[63:00]# (Data) signals are the data signals. These signals provide a 64-bit data path between the processor system
bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid
data transfer.
bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid
data transfer.