Intel G640T CM8062301002204 Benutzerhandbuch
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CM8062301002204
Processor Configuration Registers
292
Datasheet, Volume 2
2.21.26 IEUADDR_REG—Invalidation Event Upper Address
Register
This register specifies the Invalidation Event interrupt message upper address.
2.21.27 IRTA_REG—Interrupt Remapping Table Address Register
This register provides the base address of Interrupt remapping table. This register is
treated as RsvdZ by implementations reporting Interrupt Remapping (IR) as not
supported in the Extended Capability register.
treated as RsvdZ by implementations reporting Interrupt Remapping (IR) as not
supported in the Extended Capability register.
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
AC–AFh
Reset Value:
0000_0000h
Access:
RW-L
Size:
32 bits
Bit
Attr
Reset
Value
RST/
PWR
Description
31:0
RW-L
0000_000
0h
Uncore
Message Upper Address (MUA)
Hardware implementations supporting Queued Invalidations and
Hardware implementations supporting Queued Invalidations and
Extended Interrupt Mode are required to implement this register.
Hardware implementations not supporting Queued Invalidations or
Hardware implementations not supporting Queued Invalidations or
Extended Interrupt Mode may treat this field as RsvdZ.
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
B8–BFh
Reset Value:
0000_0000_0000_0000h
Access:
RW-L
Size:
64 bits
BIOS Optimal Default
0000_0000h
Bit
Attr
Reset
Value
RST/
PWR
Description
63:39
RO
0h
Reserved
38:12
RW-L
0000000h
Uncore
Interrupt Remapping Table Address (IRTA)
This field points to the base of 4KB aligned interrupt remapping
This field points to the base of 4KB aligned interrupt remapping
table.
Hardware ignores and does not implement bits 63:HAW, where
Hardware ignores and does not implement bits 63:HAW, where
HAW is the host address width.
Reads of this field returns value that was last programmed to it.
Reads of this field returns value that was last programmed to it.
11
RW-L
0b
Uncore
Extended Interrupt Mode Enable (EIME)
This field is used by hardware on Intel 64 platforms as follows:
0 = xAPIC mode is active. Hardware interprets only low 8-bits of
This field is used by hardware on Intel 64 platforms as follows:
0 = xAPIC mode is active. Hardware interprets only low 8-bits of
Destination-ID field in the IRTEs. The high 24-bits of the
Destination-ID field are treated as reserved.
1 = x2APIC mode is active. Hardware interprets all 32-bits of
Destination-ID field in the IRTEs.
This field is implemented as RsvdZ on implementations reporting
Extended Interrupt Mode (EIM) field as Clear in Extended
Capability register.
10:4
RO
0h
Reserved
3:0
RW-L
0h
Uncore
Size (S)
This field specifies the size of the interrupt remapping table. The
This field specifies the size of the interrupt remapping table. The
number of entries in the interrupt remapping table is 2^(X+1),
where X is the value programmed in this field.