HP A2Y15AV Benutzerhandbuch

Datasheet, Volume 2

115

Processor Configuration Registers 

18

RO

0b

Uncore

Clock Power Management (CPM) 
A value of 1b in this bit indicates that the component tolerates 

the removal of any reference clock(s) when the link is in the L1 

and L2/3 Ready link states. A value of 0b indicates the 

component does not have this capability and that reference 

clock(s) must not be removed in these link states.
This capability is applicable only in form factors that support 

"clock request" (CLKREQ#) capability.
For a multi-function device, each function indicates its capability 

independently. Power Management configuration software must 

only permit reference clock removal if all functions of the 

multifunction device indicate a 1b in this bit. 

17:15

RO

0h

14:12

RO-V

100b

Uncore

L0s Exit Latency (L0SELAT) 
This field indicates the length of time this Port requires to 

complete the transition from L0s to L0.
000 = Less than 64 ns
001 = 64 ns to less than 128 ns
010 = 128 ns to less than 256 ns
011 = 256 ns to less than 512 ns
100 = 512 ns to less than 1 us
101 = 1 us to less than 2 us
110 = 2 us–4 us
111 = More than 4 us
The actual value of this field depends on the common Clock 

Configuration bit (LCTL[6]) and the Common and Non-Common 

clock L0s Exit Latency values in L0SLAT (Offset 22Ch) 

11:10

RW-O

11b

Uncore

Active State Link PM Support (ASLPMS) 
Root port supports ASPM L0s and L1. 

9:0

RO

0h