Intel G645 BX80623G645 Benutzerhandbuch

202

Datasheet, Volume 2

15:13

RO

0h

12

RWS

0b

Powerg

ood

Compliance De-emphasis (ComplianceDeemphasis)
This bit sets the de-emphasis level in Polling. Compliance state if 

the entry occurred due to the Enter Compliance bit being 1b.
1 = -3.5 dB
0 = -6 dB
When the Link is operating at 2.5 GT/s, the setting of this bit has 

no effect. Components that support only 2.5 GT/s speed are 

permitted to hardwire this bit to 0b.
For a Multi-Function device associated with an Upstream Port, the 

bit in Function 0 is of type RWS, and only Function 0 controls the 

component's Link behavior. In all other Functions of that device, 

this bit is RsvdP.
This bit is intended for debug, compliance testing purposes. 

System firmware and software is allowed to modify this bit only 

during debug or compliance testing.

11

RWS

0b

Powerg

ood

Compliance SOS (compsos)
When set to 1, the TXTSSM is required to send SKP Ordered Sets 

periodically in between the (modified) compliance patterns. For a 

Multi-Function device associated with an Upstream Port, the bit in 

Function 0 is of type RWS, and only Function 0 controls the 

component's Link behavior. In all other Functions of that device, 

this bit is RsvdP. Components that support only the 2.5 GT/s speed 

are permitted to hardwire this field to 0b.

10

RWS

0b

Powerg

ood

Enter Modified Compliance (entermodcompliance)
When this bit is set to 1, the device transmits modified compliance 

pattern if the TXTSSM enters Polling. Compliance state. 

Components that support only the 2.5GT/s speed are permitted to 

hardwire this bit to 0b.

9:7

RWS-V

000b

Powerg

ood

Transmit Margin (txmargin)
This field controls the value of the non-deemphasized voltage level 

at the Transmitter pins. This field is reset to 000b on entry to the 

LTSSM Polling.Configuration substate.
Encodings:
000b

Normal operating range

001b–111b  As defined in the “Transmitter Margining” section of 

the PCI Express Base Specification 3.0, not all 

encodings are required to be implemented.

For a Multi-Function device associated with an upstream port, the 

field in Function 0 is of type RWS, and only Function 0 controls the 

component’s Link behavior. In all other Functions of that device, 

this field is of type RsvdP.
Components that support only the 2.5 GT/s speed are permitted to 

hardwire this bit to 000b.
This register is intended for debug, compliance testing purposes 

only. System firmware and software is allowed to modify this 

register only during debug or compliance testing. In all other 

cases, the system must ensure that this register is set to the 

default value.