Intel G2100T CM8063701219000 Benutzerhandbuch
Produktcode
CM8063701219000
Processor Configuration Registers
112
Datasheet, Volume 2
2.6.37
DSTS—Device Status Register
Reflects status corresponding to controls in the Device Control register. The error
reporting bits are in reference to errors detected by this device, not errors messages
received across the link.
reporting bits are in reference to errors detected by this device, not errors messages
received across the link.
B/D/F/Type:
0/1/0–2/PCI
Address Offset:
AA–ABh
Reset Value:
0000h
Access:
RW1C, RO
Size:
16 bits
BIOS Optimal Default
000h
Bit
Attr
Reset
Value
RST/
PWR
Description
15:6
RO
0h
Reserved
5
RO
0b
Uncore
Transactions Pending (TP)
0 = All pending transactions (including completions for any
0 = All pending transactions (including completions for any
outstanding non-posted requests on any used virtual channel)
have been completed.
1 = Indicates that the device has transaction(s) pending
(including completions for any outstanding non-posted
requests for all used Traffic Classes).
Not Applicable or Implemented. Hardwired to 0.
4
RO
0h
Reserved
3
RW1C
0b
Uncore
Unsupported Request Detected (URD)
This bit indicates that the Function received an Unsupported
This bit indicates that the Function received an Unsupported
Request. Errors are logged in this register regardless of whether
error reporting is enabled or not in the Device Control register. For
a multi-Function device, each Function indicates status of errors as
perceived by the respective Function.
Not Applicable or Implemented. Hardwired to 0.
Not Applicable or Implemented. Hardwired to 0.
2
RW1C
0b
Uncore
Fatal Error Detected (FED)
This bit indicates status of Fatal errors detected. Errors are logged
This bit indicates status of Fatal errors detected. Errors are logged
in this register regardless of whether error reporting is enabled or
not in the Device Control register. For a multi-Function device,
each Function indicates status of errors as perceived by the
respective Function.
Not Applicable or Implemented. Hardwired to 0.
Not Applicable or Implemented. Hardwired to 0.
1
RW1C
0b
Uncore
Non-Fatal Error Detected (NFED)
This bit indicates status of Nonfatal errors detected. Errors are
This bit indicates status of Nonfatal errors detected. Errors are
logged in this register regardless of whether error reporting is
enabled or not in the Device Control register. For a multi-Function
device, each Function indicates status of errors as perceived by the
respective Function.
Not Applicable or Implemented. Hardwired to 0.
Not Applicable or Implemented. Hardwired to 0.
0
RW1C
0b
Uncore
Correctable Error Detected (CED)
This bit indicates status of correctable errors detected. Errors are
This bit indicates status of correctable errors detected. Errors are
logged in this register regardless of whether error reporting is
enabled or not in the Device Control register. For a multi-Function
device, each Function indicates status of errors as perceived by the
respective Function.
Not Applicable or Implemented. Hardwired to 0.
Not Applicable or Implemented. Hardwired to 0.