Intel 1005M AW8063801121200 Benutzerhandbuch
Produktcode
AW8063801121200
Power Management
60
Datasheet, Volume 1
4.2.5.1
Package C0
Package C0 is the normal operating state for the processor. The processor remains in
the normal state when at least one of its cores is in the C0 or C1 state or when the
platform has not granted permission to the processor to go into a low power state.
Individual cores may be in lower power idle states while the package is in C0.
the normal state when at least one of its cores is in the C0 or C1 state or when the
platform has not granted permission to the processor to go into a low power state.
Individual cores may be in lower power idle states while the package is in C0.
4.2.5.2
Package C1/C1E
No additional power reduction actions are taken in the package C1 state. However, if
the C1E sub-state is enabled, the processor automatically transitions to the lowest
supported core clock frequency, followed by a reduction in voltage.
the C1E sub-state is enabled, the processor automatically transitions to the lowest
supported core clock frequency, followed by a reduction in voltage.
The package enters the C1 low power state when:
• At least one core is in the C1 state
• The other cores are in a C1 or lower power state
• The other cores are in a C1 or lower power state
The package enters the C1E state when:
• All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint
• All cores are in a power state lower that C1/C1E but the package low power state is
• All cores are in a power state lower that C1/C1E but the package low power state is
limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR
• All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is
enabled in IA32_MISC_ENABLES
No notification to the system occurs upon entry to C1/C1E.
4.2.5.3
Package C3 State
A processor enters the package C3 low power state when:
• At least one core is in the C3 state
• The other cores are in a C3 or lower power state, and the processor has been
• The other cores are in a C3 or lower power state, and the processor has been
granted permission by the platform
• The platform has not granted a request to a package C6/C7 state but has allowed a
package C6 state
In package C3-state, the L3 shared cache is valid.
4.2.5.4
Package C6 State
A processor enters the package C6 low power state when:
• At least one core is in the C6 state
• The other cores are in a C6 or lower power state and the processor has been
• The other cores are in a C6 or lower power state and the processor has been
granted permission by the platform
• The platform has not granted a package C7 request but has allowed a C6 package
state.
In package C6 state, all cores have saved their architectural state and have had their
core voltages reduced to zero volts. The L3 shared cache is still powered and snoopable
in this state. The processor remains in package C6 state as long as any part of the L3
cache is active.
core voltages reduced to zero volts. The L3 shared cache is still powered and snoopable
in this state. The processor remains in package C6 state as long as any part of the L3
cache is active.