Intel E7-8891 v2 CM8063601377422 Benutzerhandbuch

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CM8063601377422
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Processor Uncore Configuration Registers
112
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.2.3
SPARECTL
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
1
Bus:
1
Device: 29
Function:
1
Offset:
0x90
Bit
Attr
Default
Description
31:30
RV
0x0
Reserved.
29:29
RW_LB
0x0
DisWPQWM (diswpqwm):
Disable WPQ level based water mark, so that sparing wm is only based on 
HaFifoWM.
If DisWPQWM is clear, the spare window is started when the number of hits to 
the failed DIMM exceed max (# of credits in WPQ not yet returned to the HA, 
HaFifoWM)
If DisWPQWM is set, the spare window starts when the number of hits to the 
failed DIMM exceed HaFifoWM.
In either case, if the number of hits to the failed DIMM do not hit the WM, the 
spare window will still start after SPAREINTERVAL.NORMOPDUR timer 
expiration.
28:24
RW_LB
0x0
HaFifoWM (hafifowm):
minimum water mark for HA writes to failed rank. Actual wm is max of WPQ 
credit level and HaFifoWM. When wm is hit the HA is backpressured and a 
sparing window is started.
If DisWPQWM is clear, the spare window is started when the number of hits to 
the failed DIMM exceed max (# of credits in WPQ not yet returned to the HA, 
HaFifoWM)
If DisWPQWM is set, the spare window starts when the number of hits to the 
failed DIMM exceed HaFifoWM.
23:16
RW
0x0
SCRATCH_PAD (scratch_pad):
This field is available as a scratch pad for SSR operations
15:11
RV
-
Reserved.
10:8
RW_LB
0x0
DST_RANK (dst_rank):
Destination logical rank used for the memory copy.
7:7
RV
-
Reserved.
6:4
RW_LB
0x0
SRC_RANK (src_rank):
Source logical rank that provides the data to be copied.
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