Intel E7-8891 v2 CM8063601377422 Benutzerhandbuch

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CM8063601377422
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Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
177
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
Dual mapped as PCU IOREG
13.7.3.6
MCA_ERR_SRC_LOG
MCA Error Source Log.
MCSourceLog is used by the PCU to log the error sources. This register is initialized to 
zeroes during reset. The PCU will set the relevant bits when the condition they 
represent appears. The PCU never clears the registers-the UBox or off-die entities 
should clear them when they are consumed, unless their processing involves taking 
down the platform.
13.7.3.7
THERMTRIP_CONFIG
This register is used to configure whether the Thermtrip signal only carries the 
processor Trip information, or does it carry the Mem trip information as well. The 
register will be used by HW to enable ORing of the memtrip info into the thermtrip OR 
tree.
Type:
CFG
PortID: N/A
Bus:
1
Device: 10
Function:
2
Offset:
0xd8
Bit
Attr
Default
Description
31:0
RO_V
0x0
Power Limit Throttle Counter (PWR_LIMIT_THROTTLE_CTR):
Reports the number of times the Power limiting algorithm had to clip the power 
limit due to hitting the lowest power state available.
Accumulated DRAM throttled time
Type:
CFG
PortID: N/A
Bus:
1
Device: 10
Function:
2
Offset:
0xec
Bit
Attr
Default
Description
31:31
RWS_V
0x0
CATERR:
External error: The package sampled the CATERR# asserted (for any reason). 
It is or (bit 30, bit29); functions as a Valid bit for the other two package 
conditions. It has no effect when a local core is associated with the error.
30:30
RWS_V
0x0
IERR:
External error: The remote socket asserted IERR.
29:29
RWS_V
0x0
MCERR:
External error: The remote socket asserted MCERR.
28:16
RV
-
Reserved.
15:0
RWS_V
0x0
Core Mask (CORE_MASK):
Bit i is on if core i asserted an error.
Type:
CFG
PortID: N/A
Bus:
1
Device: 10
Function:
2
Offset:
0xf8
Bit
Attr
Default
Description
31:4
RV
-
Reserved.
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